Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-06-05
2004-03-23
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S191000
Reexamination Certificate
active
06711604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and a method for determining the sum of first and second optical binary words, each word having a number of optical bit slots.
2. Description of Related Art
In the field of all optical processing, optical signal streams are used for data processing applications. These optical streams consist of an optical pulse train that is divided into a series of bit slots. Each bit slot, which has a predetermined length within the pulse train, represents a single bit of data, with the presence or absence of an optical pulse within a bit slot representing complementary logical states. Thus, for example, the presence of an pulse may represent a binary “1”, whilst the absence of an optical pulse may represent a binary “0”, or vice versa. In this specification, therefore, we use the terminology “optical binary word” to mean a binary word represented optically in this manner.
One of the basic optical processing applications which is required is the ability to generate the binary sum of two optical binary words each word consisting of a number of bit slots.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, we provide apparatus for determining the sum of first and second optical binary words, each word having L optical bit slots, each bit slot representing a respective one of first and second logical states, the apparatus comprising a first optical logic gate which generates a first combination word representing a first logical combination of binary words applied thereto, a second optical logic gate which generates a second combination word representing a second logical combination of binary words applied thereto, offsetting means for offsetting the first and second combination words by one bit slot with respect to each other to generate first and second offset combination words, and means for repeatedly applying the previously generated first and second offset combination words to first and second logic gates which respectively generate first and second combination words representing the first and second logical combination of the binary words applied thereto, wherein the first and second offset combination words initially comprise the first and second binary words, the binary sum being given by the first combination word then each bit slot of the second combination word has the same logical state.
According to a second aspect of the present invention we provide a method for determining the sum of first and second optical binary words, each word having L optical bit slots, each bit slot representing a respective one of first and second logical states, the method comprising the steps of:
1) generating a first combination word representing a first logical combination of first and second offset combination words;
2) generating a second combination word representing a second logical combination of first and second offset combination words;
3) generating the first and second offset combination words by offsetting the first combination word by one bit slot with respect to the second combination word;
4) continuously repeating steps 1), 2) and 3) until each bit slot of the second combination word has the same logical state, wherein the first and second offset combination words initially comprise the first and second binary words, the binary sum being given by the first combination word when each bit slot of the second combination word has the same logical state.
Exemplary embodiments of an apparatus and a method of the present invention generate the sum of first and second optical binary words. This is achieved by generating first and second combination words representing first and second logical combinations of the optical binary words, using first and second optical logic gates. These optical combination words are then offset with respect to each other and recombined to generate further combination words. By repeating this process until each bit slot of the second combination word has the same logical state, the binary sum of the first and second binary words can be determined.
Typically the first and second logic gates have first and second inputs for receiving the binary words to be combined, although a single input could be utilised with the binary words to be combined being applied consecutively.
Preferably the means for repeatedly applying the previously generated first and second offset combination words to first and second logic gates comprises a connection from the output of the first logic gate to the second inputs of the first and second logic gates, and a connection from the output of the second logic gate to the first inputs of the first and second logic gates. This is effectively a feedback system, with the combination word generated at the output of each logic gate being fed back to an input of both logic gates.
Alternatively however a feed forward system can be employed in which the means for repeatedly applying the previously generated first and second offset combination words to first and second logic gates comprises N first and second optical logic gate pairs, each first and second optical logic gate pair comprising a first optical logic gate which generates a first combination word representing a first logical combination of binary words applied thereto, a second optical logic gate which generates a second combination word representing a second logical combination of binary words applied thereto, and offsetting means for offsetting the first and second combination words by one bit slot with respect to each other to generate first and second offset combination words, wherein the offsetting means is coupled to the downstream first and second optical logic gate pair such that the generated first and second offset combination words are applied to the first and second logic gates of the downstream first and second optical logic gate pair.
In the feedback system the offsetting means typically comprises an L bit slot delay line coupled to the output of the first optical logic gate and either an L+1 or an L−1 bit slot delay line coupled to the output of the second optical logic gate. Whilst any suitable method of introducing a one bit slot delay may be used, it is very difficult to introduce single bit slot delays at high bit rates. Accordingly, it is preferable to use L and either L+1 or L−1 bit delays allowing a one bit slot offset to be generated between the relevant optical binary words. Furthermore by using L and L+1 and L−1 bit slot delays, the output combination words can subsequently be fed back to the inputs of the logic gates without interfering with the previously input words.
The use of the L+1 or L−1 bit slot delay will depend on the format of the optical binary words. Thus if the first bit slot of the optical binary word represents the least significant bit of the binary numbers to be added, then the L+1 bit slot delay is used. On the other hand, if the first bit slot represents the most significant bit then the L−1 bit slot delay is used.
For ease of discussion the remainder of the specification will discuss examples in which the first bit slot represents the least significant bit of the binary numbers to be added, unless otherwise stated. Accordingly, the use of the L+1 bit slot delay will be assumed, although it will be appreciated that for a different optical binary word format the L−1 bit slot delay would be used.
Typically, in the feedback system, the connection from the first logic gate to the second inputs of the first and second logic gates comprises the L bit slot delay line, and wherein the connection from the output of the second logic gate to the first inputs of the first and second logic gates comprises either the L+1 or the L−1 bit slot delay line, although additional connections may be employed.
Preferably the feedback apparatus further comprises an optical combiner, the optical combiner having a first combiner input coupled to the L+1 bit slot delay line
Blow Keith James
Manning Robert John
Poustie Alistair James
British Telecommunications public limited company
Ngo Chuong Dinh
LandOfFree
Binary adder does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Binary adder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Binary adder will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3230148