Binary adder

Details Binary adder Binary adder

1976-01-19

1977-10-04

Malzahn, David H.

Boots, shoes, and leggings

364770, G06F 750

Patent

active

040526046

ABSTRACT:
A binary adder employs separate summing and carry circuitry within each digit to optimize the speed of operation of the adder. Carry bits of less significant digits are calculated independently of corresponding sum bits, thus allowing propagation of such carry bits to more significant digits before completion of the summation of the less significant digits.

REFERENCES:
patent: 3249746 (1966-05-01), Helbig et al.
patent: 3454751 (1969-07-01), Brastins et al.
patent: 3465133 (1969-09-01), Booher
patent: 3766371 (1973-10-01), Suzuki
patent: 3843876 (1974-10-01), Fette et al.
patent: 3932734 (1976-01-01), Parsons
J. P. Beraud, "High-Speed Four-Bit Adder", IBM Technical Disclosure Bulletin, vol. 16, No. 12, May 1974, pp. 3950-3951.

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