BiMOS logical circuit

Details BiMOS logical circuit BiMOS logical circuit

1987-10-09

1989-02-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307570, H03K 1901, H03K 19003, H03K 19082, H03K 19094

Patent

active

048048690

ABSTRACT:
The invention is a BiMOS logical circuit having a reduced number of components and increased operating speed. First and second MOS transistors are provided for, respectively, driving first and second bipolar transistors. The gates of these MOS transistors are, respectively, connected to the bases of the second and first bipolar transistors. The input terminal is connected to the gates of the MOS transistors.

REFERENCES:
patent: 4713796 (1987-12-01), Ogiue et al.
patent: 4719370 (1988-01-01), Sugimoto
patent: 4719373 (1988-01-01), Masuda et al.
patent: 4733110 (1988-03-01), Hara et al.
Katsumi Ogiue et al., IEEE Journal of Solid-State Circuits, "13 ns, 500 mW, 64kbit EclRAM Using Hi-Bicmos Technology", vol. SC-21, No. 5, Oct. 1986.

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