BIMOS logic gate

Details BIMOS logic gate BIMOS logic gate

1986-01-13

1987-03-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307454, 307270, 307570, H03K 1901, H03K 19082, H03K 19094

Patent

active

046492950

ABSTRACT:
A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d.c. power dissipation. A first MOS transistor circuit is coupled to the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between an input terminal and both the upper transistor and the first MOS transistor circuit for providing a high impedance at the input and for biasing both the upper transistor and the first MOS transistor circuit, wherein the first circuit is biased with a larger voltage than the upper transistor for improving the switching speed of the output signal.

REFERENCES:
patent: 4301383 (1981-11-01), Taylor
patent: 4612458 (1986-09-01), Vasseghi et al.
Lin et al, "Complementary MOS-Bipolar Transistor Structure", IEEE Trans. Electron Devices, vol. ED-16, No. 11, 11-1969, pp. 945-951.

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