BiMos input circuit

Details BiMos input circuit BiMos input circuit

1987-10-30

1989-08-15

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307458, 307475, 307581, H03K 1902, H03K 19007, H03K 19084

Patent

active

048577669

ABSTRACT:
An ECL input circuit which receives an ECL input signal and which generates, in response to the input signal, a CMOS-compatible output signal. The input circuit includes a bipolar transistor, having its emitter region adapted to receive the ECL input signal, having its collector region coupled to a first current source, and having its base region connected to a second current source. The circuit further includes an output circuit which is coupled to the collector region of the bipolar transistor for providing the CMOS-compatible signal.

REFERENCES:
patent: 3739238 (1973-06-01), Hara
patent: 3827034 (1974-07-01), Colaro
patent: 3955269 (1976-05-01), Magdo et al.
patent: 4048649 (1977-09-01), Bohn
patent: 4085417 (1978-04-01), Ochi
patent: 4256984 (1981-03-01), Kojima
patent: 4264941 (1981-04-01), London
patent: 4314267 (1982-02-01), Bergeron et al.
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4529894 (1985-07-01), Chan et al.
IBM Technical Disclosure Bulletin, "Bipolar and FET Integration on a Common Chip", vol. 15, No. 12, May 1973.
"Transistor Schottky-Barrier-Diode Integrated Logic Circuit" IEEE Journal of Solid-State Circuits, vol. SC-4, No. 1, Feb. 1969.

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