Bimodal slurry system

Details Bimodal slurry system Bimodal slurry system

2002-04-25

2003-10-28

Marcheschi, Michael (Department: 1755)

Abrasive tool making process, material, or composition

With inorganic material

Metal or metal oxide

C051S307000, C051S308000, C051S298000, C106S003000

Reexamination Certificate

active

06638328

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to polishing slurries and more particularly to polishing slurries with a bimodal mean particle size useful for chemical mechanical polishing (CMP) of semiconductor wafers including copper metal interconnects formed in low-k dielectric material.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers may be accomplished using various fabrication techniques including oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Planarization, for example, is an increasingly important in semiconductor manufacturing technology. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe restraints on the degree of planarity of a semiconductor wafer processing surface. Excessive degrees of process surface nonplanarity will affect the quality of several semiconductor process including, for example, in a photolithographic process, the positioning the image plane of the process surface within an increasingly limited depth of focus window to achieve high resolution semiconductor feature patterns.
One planarization process is chemical mechanical polishing (CMP). CMP is increasingly being used for planarizing dielectrics and other layers, including applications with increasingly stringent critical dimension semiconductor fabrication processes. CMP planarization is typically used several different times in the manufacture of a multi-layer semiconductor device. For example, CMP is used as one of the processes in preparing a layered device structure in a multi-layer device for subsequent processing. CMP is used to remove excess metal after filling conductive metal interconnects such as vias and trench lines with metal to electrically interconnect the several layers and areas that make up a multi-layer semiconductor device.
In a typical process for forming conductive interconnections in a multi-layer semiconductor device a damascene process is used to form vias and trench lines for interconnecting different layers and areas of the multilayer device. Vias (e.g., V
1
, V
2
etc. lines) are generally used for vertically electrically interconnecting semiconductor device layers and trench lines (e.g., M
1
, M
2
, etc. lines) are used for electrically interconnecting semiconductor device areas within a layer. Vias and trench lines are typically formed as part of a damascene process. Although there are several different methods for forming damascene structures, one typical method generally involves patterning and etching a semiconductor feature, for example a via opening within an insulating dielectric layer to make contact with a conductive area within an underlying layer of the multilayer device. The via opening (plug) may then be filled with for example, copper to form a via (plug) followed by a CMP step to remove excess metal deposited on the insulating dielectric layer surface and to planarized the surface for a subsequent processing step. A second insulating dielectric layer is then deposited followed by patterning and etching the second insulating dielectric layer to form a trench opening situated over the via. The trench opening is then filled with a metal, for example, copper, to form trench lines (intra-layer horizontal metal interconnections). A second CMP step is then carried out similar to the first CMP step to remove excess metal and to planarize the process wafer surface in preparation for further processing.
CMP is widely accepted as the preferred process for many planarization processes including planarizing copper filled trench lines. CMP is the method of choice particularly for smaller device fabrication technologies including dimensions of less than about 0.27 micron. CMP generally includes placing a process surface of the wafer in contact against a flat polishing surface, and moving the wafer and the polishing surface relative to one another. The polishing action is typically aided by a slurry which includes for example, small abrasive particles such as colloidal silica (SiO
2
) or alumina (Al
2
O
3
) that abrasively act to remove a portion of the process surface. Additionally, the slurry may additionally include chemicals that react with the process surface to assist in removing a portion of the surface material, the slurry typically being separately introduced between the wafer surface and the polishing pad. During the polishing or planarization process, the wafer is typically pressed against a rotating polishing pad. In addition, the wafer may also rotate and oscillate back and forth over the surface of the polishing pad to improve polishing effectiveness.
Typically CMP polishing slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium. There are various mechanisms disclosed in the prior art by which metal surfaces can be polished with slurries. The metal surface may be polished using a slurry where a surface film is not formed causing the process to proceed by mechanical removal of metal particles. In using this method, the chemical dissolution rate should be slow in order to avoid wet etching. A more preferred mechanism is, however, one where a thin abradable layer is continuously formed by reaction between the metal surface and one or more components in the slurry such as a complexing agent and/or a film forming layer. The thin abradable layer is then removed in a controlled manner by mechanical action. Once the mechanical polishing process has stopped a thin passive film remains on the surface and controls the wet etching process. Controlling the chemical mechanical polishing process is much easier when a CMP slurry polishes using this mechanism.
There are also several different types of slurries used in the CMP process. The most common abrasives used are silica (SiO
2
), alumina (Al
2
O
3
), ceria (CeO
2
), titania (TiO
2
), and zirconia (ZrO
2
). The abrasives are typically formed using two different methods that result in fumed and colloidal abrasives. Fumed abrasives include agglomerated particles that are larger in size than the dispersed, discrete particles of colloidal abrasives. For the same solids concentration, the removal rate using a fumed abrasive is higher than that using a colloidal abrasive due to sharp edged particle features and a broader particle size distribution in fumed abrasives. For the same reasons, the defect density using a fumed abrasive also tends to be higher.
To minimize defect formation, the colloidal abrasives having a more uniform particle size distribution are preferred. However, to achieve the same material removal rate as using a fumed abrasive, the solids concentration of a colloidal slurry must be almost three times higher. The higher required solids concentration undesirably increases the cost of the slurry.
One particular problem with the prior art methods of CMP involve the unique problems inherent in the increasing use of low-k(dielectric constant) materials as an inter-layer dielectric (ILD) together with copper filled vias and copper interconnect lines (trench lines). The low-k insulating dielectrics generally tend to be highly porous in an effort to lower dielectric constants lower than about 3.0 thereby lowering capacitive effects in the ILD. Lower capacitances are required to reduce signal delay times as feature sizes decrease. Additionally, copper has become the conductor of choice for metal interconnects as device sizes decrease primarily due to low resistivity. Several different materials have been proposed

Affiliated with

Also associated with

Rating

Bimodal slurry system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bimodal slurry system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bimodal slurry system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3137609