Bilingual CMOS to ECL output buffer

Details Bilingual CMOS to ECL output buffer Bilingual CMOS to ECL output buffer

1988-09-20

1989-12-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307451, H03K 19092, H03K 1716, H03K 19094

Patent

active

048900192

ABSTRACT:
The present invention provides an output buffer that converts a standard CMOS signal from the (0, +5) volt domain into a standard ECL signal in the (-0.8, -1.6) volt domain. This buffer circuit may be included as a part of a CMOS integrated circuit. The overall CMOS chip operates in the standard CMOS voltage range, but the ECL output buffer produces output levels in the standard ECL range. The buffer uses a pair of CMOS transistors (e.g., p-channel devices formed in N-wells) with the wells in which they are formed grounded and an input transistor with the well in which it is formed set at V.sub.DD (+5V). The first "grounded-well" transistor responds to the state of the input transistor to switch the second grounded-well (output) transistor on or off. Depending on its state, the output transistor contributes current or not to a voltage divider to set the appropriate ECL voltage level at the output of the buffer.

REFERENCES:
patent: 4453095 (1984-06-01), Wrathall
patent: 4538076 (1985-08-01), Shimada
patent: 4563601 (1986-01-01), Asano et al.
patent: 4704549 (1987-11-01), Sanwo et al.
patent: 4739193 (1988-04-01), Doty, II
patent: 4763022 (1988-08-01), Sheldon

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