Bilinear decimator with error compensation

Image analysis – Image transformation or preprocessing – Changing the image coordinates

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

245127, 348458, G06K 932

Patent

active

058622683

ABSTRACT:
A bilinear decimator converts an input data sequence representing a high resolution image formed by N horizontal pixel lines to an output data sequence representing a lower resolution image formed by P horizontal pixel lines where N>P. The decimation ratio P/N can be any rational fraction. When the decimation ratio reduces to the form 1-(1
), the decimator computes the each output sequence data value as a simple weighted average of pixel data values for two vertically adjacent high resolution image pixels. When the decimation ratio is other than of the form 1-(1
), the decimator adds additional terms to the computation of output pixel data values when necessary to compensate for aliasing errors.

REFERENCES:
patent: 4204227 (1980-05-01), Gurley
patent: 4677483 (1987-06-01), Dischert et al.
patent: 5019904 (1991-05-01), Campell
patent: 5253041 (1993-10-01), Wine et al.
patent: 5268751 (1993-12-01), Geiger et al.
patent: 5469222 (1995-11-01), Spragne

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Bilinear decimator with error compensation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bilinear decimator with error compensation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bilinear decimator with error compensation will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1253305

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.