Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-11-06
2004-06-01
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S692000
Reexamination Certificate
active
06743642
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the manufacture of magnetoresistive random access memory (MRAM) cells. More particularly, this invention relates to a method of manufacturing such MRAM cells using a bilayer CMP process to improve the interficial roughness between magnetic layers.
BACKGROUND OF THE INVENTION
Magnetoresisteive random access memory (MRAM) has the advantages of non-volatility, capability of three-dimensional cell packing, low power consumption, simpler and cheaper process compared to conventional DRAM and FLASH memory. The architecture for MRAM comprises a plurality or array of memory cells and a plurality of digit and bit line intersections. The MRAM cell generally used is composed of a magnetic tunnel junction (MTJ), and isolation transistor, and the intersection of digit and bit lines. An interconnect stack connects the isolation transistor to the MTJ device, to the bit line, and to the digit line used to create part of the magnetic field for programming the MRAM cell.
MRAM uses the relative orientation of the magnetization in ferromagnetic materials to store information. Optimal performance of magneto-resistive tunnel junction devices requires smooth tunnel barriers. The relative orientation of the magnetization can be corrupted by surface roughness. This corruption of the magnetization is known as “Neel coupling,” and is the remnant magnetism due to the roughness of the interfacial surface as shown in
FIG. 1. A
rough tunnel barrier induces Neel coupling which, in effect creates an offset in the switching field of the magneto-resistive device thereby reducing the operating margin of the device in a memory array. In addition, there may be a possibility of metal shorting through the tunneling junction during magnetic stack deposition when the tunneling junction thickness is in the order of the surface roughness. In practice such roughness occurs despite the use of chemical mechanical polishing (CMP) of the substrate prior to deposition of the magnetic tunnel junction metal stack.
The degree of smoothness following CMP is dependent on the type of material used for the barrier layer. The term barrier here refers to the diffusion resistance of this layer to metallic contamination from the wiring conductor. This distinguishes the function of this barrier layer from the device electron tunnel barrier. One common material for the barrier layer is tantalum nitride (TaN). Other common materials are ruthenium (Ru), tantalum (Ta) and titanium nitride (TiN) implemented as single layers or also in combination to achieve the smooth interfaces to eliminate the deleterious effect of Neel coupling.
One practical ramification of the buffer layer used beneath the metal stack is that it must be removed during the device patterning to isolate the devices. In general it is difficult to etch TaN, for example with high selectivity to an underlying dielectric material or also any exposed copper used in the wiring level below the magnetoresistive device. In addition, it is difficult to uniformly polish a thin metal layer to achieve both a smooth surface and commensurately a uniform remaining thickness over the wafer surface.
Thus, there is a need in the art for a method of manufacturing MRAM cells which minimizes such surface roughness and therefore eliminates the Neel coupling and metal shorting problems described above. There is also a need in the art for a process that provides a smooth surface while reducing the non-uniformity of the remaining metal thickness.
SUMMARY OF THE INVENTION
The problems described above are addressed through use of the present invention, which is directed to a method for fabricating a magnetoresistive random access memory cell, comprising the steps of providing a semiconductor substrate including at least one conductor embedded in a dielectric material, the top surface of the conductor being coplanar with the top surface of the dielectric material, depositing a first material on the conductor and the dielectric material; depositing a second material on the first material, wherein the second material has a polish rate faster than the first material; essentially removing the second material by chemical mechanical polishing; depositing a first magnetic layer stack, a non-magnetic tunnel junction barrier layer, and a second magnetic layer; and patterning the first material, the first magnetic layer stack, the non-magnetic tunnel junction barrier layer, and the second magnetic layer by a lithographic process.
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Costrini Gregory
Hummel John
Krishnan Mahadevaiyer
Low Kia-Seng
Nhu David
Pepper Margaret A.
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