Bifurcated method and apparatus for floating point addition with

Details Bifurcated method and apparatus for floating point addition with Bifurcated method and apparatus for floating point addition with

1984-02-24

1987-01-27

Malzahn, David H.

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G06F 750

Patent

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046398872

ABSTRACT:
Apparatus for decreasing the latency time associated with floating point addition and subtraction in a computer, using a novel bifurcated, pre-normalization/post-normalization approach that distinguishes between differences of floating point exponents.

REFERENCES:
patent: 3814925 (1974-06-01), Spannagel
patent: 4488252 (1984-12-01), Vassar
Earlen et al., "Exponent Differences and Preshifter" IBM Tech. Disclosure Bulletin, vol. 9, No. 7, Dec. 1966, pp. 848-849.
Levine, "Fraction Addition or Subtraction or Comparison Overlap with Characteristic Comparison" IBM Tech. Disclosure Bulletin vol. 15, No. 7, Dec. 1972, p. 2162.
Agerwala et al, "Floating Point Addition and Subtraction Enhancement" IBM Tech. Disclosure Bulletin vol. 24, No. 1B, Jun. 1981, pp. 722-774.

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