Oscillators – With frequency adjusting means – With voltage sensitive capacitor
Reexamination Certificate
2002-12-19
2004-06-08
Poscal, Robert (Department: 2817)
Oscillators
With frequency adjusting means
With voltage sensitive capacitor
C331S1170FE
Reexamination Certificate
active
06747523
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the invention is in the field of semiconductor voltage controlled oscillators.
2. Related Art
In the field of wireless communication, such as radio frequency (“RF”) communication, data signals are modulated over a carrier signal prior to transmission. Typically, the carrier signal used for RF communication is a sine wave. Thus, an RF signal can generally be represented by the following equation:
A
sin (&ohgr;
t
+&phgr;) (Equation 1)
where A is the magnitude of the signal, &ohgr; is the frequency of the signal, and &phgr; is the phase of the signal.
The carrier signal (or sine wave) is generated by an oscillator. For example, a typical oscillator used to generate a sine wave for RF communication is a voltage controlled oscillator (“VCO”). In phase modulation, the data signals are “encoded” into the sine wave by varying the phase component of the sine wave in accordance with the data signals. However, various noise sources can alter the phase component of the sine wave, e.g., by causing fluctuations in the phase. This disturbance upon the phase of the sine wave is commonly referred to as “phase noise.” Such phase noise is undesirable because it deteriorates the data signals which are encoded into the sine wave. In some cases, the phase noise becomes intolerable, when, for example, the signal-to-noise ratio (“S/N”) becomes so small that demodulation of the data from sine wave signal becomes difficult or impossible.
Three primary sources of phase noise include supply voltage fluctuations, ground fluctuations, and component noise due to thermal variations and/or due to frequency variations (“flicker” noise) in active and passive components. While component noise has been addressed to some degree with current devices employing active and passive components, noise due to supply voltage fluctuations and noise due to ground fluctuations remain as problems which must be addressed in any VCO implementation.
A common disadvantage shared by conventional VCOs is the limited driving capabilities at their output nodes. As a result, complex and expensive buffer circuits connected to the output nodes of conventional VCOs are typically used for driving large loads. Use of such complex and expensive buffer circuits, however, increases manufacturing costs and device size, both of which are undesirable. Another disadvantage with the use of complex buffer circuits in conventional VCOs is the large amount of current drawn by these complex buffer circuits.
Accordingly, there is a need in the art for a voltage controlled oscillator which reduces the effects of noise due to supply voltage fluctuations and ground fluctuations. Furthermore, there is a need in the art for a voltage controlled oscillator capable of driving a large load and having reduced current consumption.
SUMMARY OF THE INVENTION
The present invention is directed to a BiFET voltage controlled oscillator (“VCO”). The invention overcomes the need in the art for a VCO which reduces the effects of noise due to supply voltage fluctuations and to ground fluctuations while also overcoming the need in the art for driving a large load with reduced current consumption.
According to one exemplary embodiment, a BiFET VCO circuit comprises a VCO core circuit, first and second bipolar transistors, and first and second FETs. The VCO core circuit is connected across a first node and a second node. The VCO core circuit may, for example, comprise first and second varactors, and an inductor. The anode of the first varactor is connected to the first node while the anode of the second varactor is connected to the second node, and the cathode of the first varactor is tied to the cathode of the second varactor. A tuning voltage is also connected to the cathode of the first varactor and the cathode of the second varactor. The inductor is connected across the first node and the second node.
The first and second bipolar transistors are configured as a differential pair where the base of the first bipolar transistor is connected to the second node, the collector of the first bipolar transistor is connected to the first node, the base of the second bipolar transistor is connected to the first node, and the collector of the second bipolar transistor is connected to the second node. The emitters of the first and second bipolar transistors are also coupled to ground. The first and second FETs are configured in a common-gate configuration where the gate of the first FET is connected to the gate of the second FET, the source of the first FET is connected to the first node, and the source of the second FET is connected to the second node. A reference voltage is supplied to the gates of the first and second FETs. The drain of the first FET comprises a first output of the BiFET VCO circuit, while the drain of the second FET comprises a second output of the BiFET VCO circuit.
With this configuration, the effects of fluctuations in the supply voltage and fluctuations in the ground upon the operation of BiFET VCO circuit is significantly reduced or eliminated, and thus the voltages at the first and second nodes are stable. Furthermore, each of the first and second outputs generated by BiFET VCO circuit is capable of driving a large load without loading down the voltages at the first and second nodes, further increasing the stability of the first and second nodes. Moreover, the total current drawn by BiFET VCO circuit in operation is significantly reduced over conventional solutions because complex and expensive buffer circuits are not required to drive large loads at the first and second outputs. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
REFERENCES:
patent: 6317008 (2001-11-01), Gabara
patent: 6411171 (2002-06-01), Itoh
patent: 2002/0014925 (2002-02-01), Ochiai
Ma Pingxi
Racanelli Marco
Chang Joseph
Farjami & Farjami LLP
Newport Fab LLC
Poscal Robert
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