Patent
1992-04-21
1994-12-27
Richardson, Robert L.
395550, G06F 1300
Patent
active
053773250
ABSTRACT:
A bidirectional wait control system for controlling data movement between a slower-speed host module and a faster-speed slave module by means of a bus interface, comprises: a first wait control signal generating means in the host module, capable of generating a first wait control signal synchronizing with that of the bus interface; a second wait control signal generating means in the slave module, responsive to the first wait control signal, capable of generating a second wait control signal synchronizing with that of the bus interface; and means, upon each module having been presented with the wait control signal from the other module, for terminating data movement between the host module and the slave module.
REFERENCES:
patent: 4607348 (1986-08-01), Sheth
patent: 5222229 (1993-06-01), Fukuda et al.
Acer Incorporated
Richardson Robert L.
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