Electricity: power supply or regulation systems – In shunt with source or load – Using a three or more terminal semiconductive device
Reexamination Certificate
2002-09-09
2004-03-16
Sterrett, Jeffrey (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using a three or more terminal semiconductive device
C323S226000, C323S270000, C323S274000, C363S062000
Reexamination Certificate
active
06707280
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
1. Field of the Invention
The present invention generally relates to voltage regulators and more particularly to voltage regulators capable of sinking and sourcing current and regulating an output voltage to one half the level of an input voltage.
2. Description of the Related Art
Today's high speed DRAMS, such as DDR DRAMs, operate at very high clock frequencies. The data lines of a data bus between a CPU and DDR DRAMs require careful design to maintain signal quality, e.g., minimize signal reflection and ringing. This usually entails some form of line termination and matching of the drivers to the line impedance.
FIG. 1A
shows a representative data line of a data bus in a DDR DRAM system. The data line
13
has a source resistor R
s
14
of about 10 &OHgr;. In addition, the data line has a termination resistor R
T
15
with a value of about 56 &OHgr;. A line driver
12
operates from a supply voltage of VDDQ
11
, typically 2.5 V. A pair of line receivers, exemplified by buffers
16
and
17
, is connected to the receiving end of the data bus line
13
. The negative input of each buffer
16
,
17
is usually connected to a reference voltage
18
, whose preferred value is exactly one half of VDDQ, or 1.25V.
When the line driver
12
output is high, i.e., substantially close to 2.5V, the power dissipation of the data bus line is VDDQ
2
/(R
S+R
T
), or about 95 mW. When the line driver
12
output is low, the power dissipation is 0 Watts. Assuming the line driver
12
has an equal chance of being either high or low, the average power dissipation is about 47.5 mW. If there are
110
such data lines (not uncommon in a large DRAM system), the total power needed for the data bus is about 5.2 Watts.
FIG. 1B
shows a termination scheme similar to that of
FIG. 1A
, except that the termination resistor
25
is connected to a regulated voltage VTT
29
, which has a value that is one half of VDDQ level. Line driver
22
is still powered from a voltage VDDQ
21
, or 2.5V. The source resistor
24
of data line
23
is 10 &OHgr;. The termination resistor
25
is 56 &OHgr;and buffers
26
and
27
are connected to the receiving end of data bus line
23
.
When the line driver
22
output is high, i.e., close to 2.5V, the power dissipation of the data line is (VDDQ−VTT)
2
/(R
S
+R
T
), or about 24 mW. When line driver output is low, i.e., close to 0 V, the power dissipation is VTT
2
/(R
S
+R
T
), or 24 mW. Therefore, the average power dissipation is 24 mW and for
110
similarly terminated lines the total power is about 2.6 Watts.
From the above calculations, it is clear that connecting the termination resistor to a termination voltage of one-half of VDDQ reduces power dissipation by 50%. In a typical DRAM system, with as many as
110
lines, a savings of 2.6 W results, if a high-efficiency regulator is used to generate the termination voltage. However, in order to achieve this power savings, the termination voltage VTT regulator is required to both sink and source current. If there are more low-state lines than high-state lines, the VTT regulator sends (sources) current to the data bus system. On the other hand, if there are more high-state lines than low-state lines, the VTT regulator receives (sinks) current from the data bus system.
FIG. 2
shows a conventional synchronous buck converter
30
for providing a regulated termination voltage VTT. A buck converter
30
includes a operational amplifier (OP-AMP)
33
, a PWM controller
34
, a pair of MOSFET switches
35
and
36
, an inductor
37
, and an output capacitor
38
. The negative input of OP-AMP
33
is connected to the termination voltage VTT output node
39
. Two resistors
31
and
32
, each having a typical value of 51 k&OHgr;, are connected between the VDDQ supply voltage and ground and the positive input of OP-AMP
33
connects to the junction of the resistors
31
and
32
. This causes the positive input of the OP-AMP
33
to have a voltage of one half of VDDQ. The OP-AMP feedback loop, which includes PWM
34
, switches
35
and
36
, and inductor
37
, operates to make the voltage difference between the positive and negative input as close to zero as possible, so that the negative input and therefore VTT are regulated to substantially close to one half of the VDDQ voltage.
Further, it is well known by those skilled in the art that a buck converter, operating in a continuous inductor current mode, is capable of both sourcing current to and sinking current from its output. Specifically, if a greater number of lines are low, the buck converter
30
supplies positive output current to the VTT voltage
39
, and thus to the data bus lines, which causes the voltage VTT to drop slightly from 1.25 Volts. On the other hand, if a greater number of lines are high, a net current flows from the data bus lines to VTT capacitor
38
, which causes the VTT voltage to rise slightly above 1.25V. The buck converter
30
then operates as a boost converter, in the reverse direction, pumping current from capacitor
38
back to VDDQ via transistor switch
35
or its body diode.
The bi-directional current flow of a synchronous buck converter is illustrated in the waveforms of
FIGS. 3A-3D
.
FIG. 3A
shows the turn-on pulses of switch
35
Ql. During switch
35
turn-on time, switch
36
Q
2
is turned off.
FIG. 3B
shows the turn-on pulses of switch
36
, which correspond to the turn-off time of switch
35
.
If there is a net outflow of current from the VTT to the data bus, the buck converter
30
sources a positive output current, Iout.
FIG. 3C
shows the inductor current waveform when buck converter
30
is sourcing an output current to VTT
39
. During switch
35
turn-on time, inductor current lout ramps up with a rate of about (VDDQ−VTT)/L Amps/second. During switch
35
turn-off time (turn-on time of switch
36
), the inductor current lout ramps down with a rate of about VTT/L Amps/second. Because VTT is approximately ½ VDDQ, the ramp up and ramp down rates are approximately equal.
If there is a net inflow of current, buck converter
30
receives current from VTT
39
, behaving like a boost converter in the reverse direction.
FIG. 3D
shows the inductor current waveform when buck converter
30
is sinking current. When switch
36
turns on, inductor current builds up its magnitude in a reverse direction. For example, Iout ramps from −0.45A to−0.55A. During switch
36
off time, the reverse inductor current flows from output capacitor
38
back to VDDQ, through the conduction of switch
35
and its body diode. The reverse inductor current decreases its magnitude, since it flows into a higher voltage, VDDQ.
A synchronous buck converter has a very high power conversion efficiency but requires a power inductor which increases the space and cost of the system. Furthermore, the inductor has a leakage magnetic field which generates electromagnetic noise in other components and circuits in close proximity to the inductor.
Thus, there is a need for a regulator circuit that uses no inductor components, but is capable of sinking and sourcing current while providing a regulated termination voltage.
BRIEF SUMMARY OF THE INVENTION
One embodiment of the present invention includes a voltage regulator for providing a bidirectional current and a regulated voltage to a load. The voltage regulator includes a voltage divider circuit, a first linear regulator and a second linear regulator. The voltage divider circuit is configured to provide a regulated output voltage that is approximately half of an input voltage when the output voltage is within a voltage range set by a first predetermined level and a second predetermined level, and to provide current to the load and receiving current from the load, as needed by the load. The first linear regulator is connected to receive the input voltage, and is configured to provide additional current to the load if the regulated output voltage falls to the first predetermined level and to clamp the output voltage at the first predete
Liu Kwang H.
Negru Sorin L.
Shih Fu-Yuan
Arques Technology, Inc.
Dechert LLP
Diepenbrock III Anthony B.
Sterrett Jeffrey
LandOfFree
Bidirectional voltage regulator sourcing and sinking current... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bidirectional voltage regulator sourcing and sinking current..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bidirectional voltage regulator sourcing and sinking current... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3212733