Electrical pulse counters – pulse dividers – or shift registers: c – Pulse counting or dividing chains – Using bistable regenerative trigger circuits
Patent
1982-09-16
1985-04-02
Anagnos, Larry N.
Electrical pulse counters, pulse dividers, or shift registers: c
Pulse counting or dividing chains
Using bistable regenerative trigger circuits
377 69, 377104, 377107, 377126, H03K 2304, H03K 2308, G11C 1928
Patent
active
045091838
ABSTRACT:
A linear array of bistable data latches and logic gates arranged to count the binary transitions, both low to high and high to low, of a clock signal and provide a threshold style output code, characterized along the array by high logic states on one side of the threshold point and low logic states on the opposite side. Each latch in the array is permitted to set when a clock transition occurs after the preceding latch has set or to reset when a clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable logic may be included along with direct set/reset inputs in order to accomplish parallel and/or ripple preset/clear functions or other output code modifications.
REFERENCES:
patent: 3277380 (1966-10-01), Paufve
patent: 3295063 (1966-12-01), Felcheck et al.
patent: 3548167 (1970-12-01), Emde
patent: 3588475 (1971-06-01), Scott
patent: 4075464 (1978-02-01), Davies, Jr.
Cheng et al., "Up/Down Ripple Counter", IBM Tech. Discl. Bull., vol. 24, No. 9, pp. 4709-4713, 2/82.
Anagnos Larry N.
Wright Helene R.
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