Bidirectional socket stimulus interface for a logic simulator

Details Bidirectional socket stimulus interface for a logic simulator Bidirectional socket stimulus interface for a logic simulator

1995-10-27

2002-07-16

Follansbee, John A. (Department: 2154)

Data processing: software development, installation, and managem

Software program development tool

Testing or debugging

C712S037000

Reexamination Certificate

active

06421823

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bidirectional socket stimulus interface for a logic simulator, and more particularly, to a bidirectional socket stimulus interface which allows input stimuli to be provided interactively from a keyboard, from a data file, or from a UNIX® socket directly to the logic simulator. The system of the invention also allows the user to provide input stimuli which behaviorally model complex logic systems that the logic simulator model is part of by basing the state of the next input vector on the present state of the logic simulator.
2. Description of the Prior Art
When designing integrated circuits for performing particular functions, design engineers have traditionally drawn schematic diagrams of the proposed circuit setting forth all of the elements and interconnections necessary for the circuit to perform the desired functions. From the schematic diagrams, prototype circuits were built and tested. Before the advent of computer aided design (CAD) systems, the prototype of the circuit was actually built using techniques such as wire-wrapping and the like. The resulting prototype circuit was then tested by applying different combinations of input signals (input vectors) to the circuit and checking the output of the circuit on a device such as an oscilloscope. Errors in the circuit design were found when the outputs were not those desired, and the design flaw or improper connection was typically manually tracked down by careful examination of the circuit schematic and prototype wiring. Once the design flaw or improper connection was found, the prototype circuit was rebuilt and retested. This circuit design process was very time-consuming and tedious, and accordingly, design engineers sought different methods for converting the circuit schematic into a circuit which performs the desired functions.
Computer aided design (CAD) systems have greatly helped design engineers in this circuit design process. CAD systems allow the design engineer to prepare the circuit schematics on the computer, to lay out the circuit for implementation on a circuit board, and to test the circuit using logic simulation techniques. Logic simulators thus allow the design engineer to test the proposed circuit design without actually building the prototype. This is accomplished by having the design engineer specify as input to the logic simulator the elements and nodes of the circuit and the signals expected at those nodes for particular inputs. This information is determined directly from the circuit schematic diagram and is typically input into the logic simulator as an input file. The logic simulator runs this data through a model of the proposed circuit to generate the outputs of the simulated circuit. Such logic simulators are limited, however, in that they do not provide for use of a behavioral model which characterizes the circuit and thus do not allow the simulation input vectors for testing the circuit design to be automatically extracted from the circuit schematic diagram. Instead, the design engineer has had to painstakingly design and implement the simulation model and to create the input vector file.
An example of a logic simulator of the type described above is shown in FIG.
1
. As shown, a simulation model
100
of the circuit being tested is provided to a logic simulator, such as a switch-level logic simulator
102
, which simulates the functions of the circuit represented by the simulation model
100
. Switch-level logic simulator
102
may include node evaluation algorithms which make it possible for the logic simulator
102
to simulate operation of circuits modeled entirely with bidirectional switches. Switch-level logic simulators are thus important tools for circuit design, for whenever a design engineer stops using classic logic gates and starts using dynamic or transfer gate logic, a switch-level logic simulator becomes necessary. This is because a conventional logic simulator cannot model all of the complex interactions which take place between non-classical transistor connections. Accordingly, the description herein is directed towards a system including a switch-level logic simulator.
The simulation model
100
of the circuit must be generated by the design engineer before a simulation can take place. This means that all of the elements, interconnections and nodes for a circuit design must be gathered together and converted into an input data file which is in a format acceptable to the logic simulator
102
. Typically, the input data file contains a file having one entry for every transistor in the design, where the file is described using node numbers only, and also includes a file containing the node number to signal name mapping. The model is generated by converting the input files into a binary database which can be loaded directly into the logic simulator
102
. In other words, the logic simulator
102
reads the input data file and formats it into a memory based data structure that expresses the connectivity of the circuit model. This data structure is then stored as a file in the logic simulator
102
and is referred to as the logic simulator database.
In addition to the simulation model
100
, it is necessary to generate an input vector file
104
of input stimuli so that operation of the circuit can be simulated. The input vector file
104
contains all of the desired input stimulus patterns (vectors) and logic simulator control commands. The input vector file
104
may also contain any output assertions that predict the desired behavior of the circuit. The inclusion of the output assertions in an input vector file
104
allows the input vector set to act as a regression test and greatly simplifies post-processing of a simulation run. In addition to input stimuli, known faults may be inserted into the input vector file
104
so that the logic simulator
102
may be used as a fault simulator.
When the logic simulator
102
is run, two output files are typically created. The first file is the simulator list file, while the second is the raw data file. The simulator list file is typically an ASCII file which lists any simulator generated status messages as well as any assertion failures. The raw data file, on the other hand, is typically a non-ASCII file which contains the node transitions for every node in the logic simulator model for all of the time steps in the simulation. The raw data files are used by the logic simulator post-processor to display any requested node for any time period. In particular, the post-processor translates the raw data file into a form which is viewable by the user. The user can preferably control which signals and which time steps are displayed.
In addition, the logic simulator
102
may include a file which contains the values of all the nodes at a particular point in time. This file can be used to reset a simulation to a known state and is commonly used when developing an input vector file to save a state of the simulation model, such as a reset state, which can be restored over and over throughout a simulation. The ability to restart at a known point makes the process of developing an input vector file
104
easier.
As part of the test vector creation and simulation techniques described above, design engineers wrote detailed behavioral descriptions of both the circuit and the outside world as test and circuit specific vectors. Previous simulation methodologies provided two methods of creating such circuit specific vectors. In the first method, the input vector file
104
is created by the design engineer by hand by specifying the input vectors necessary to excite the circuit in accordance with the truth table. In other words, the design engineer has had to specify the portions of the truth table of the circuit which was to be tested by a particular simulation and has had to prepare the necessary input file
104
taking into account the capacitances of the circuit, propagation delays and the like so that the simulation would perform correctly. This process requ

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