Bidirectional parallel data port having multiple data transfer r

Details Bidirectional parallel data port having multiple data transfer r Bidirectional parallel data port having multiple data transfer r

1995-05-26

1998-01-20

Lee, Thomas C.

395851, 395852, 395849, G06F 1300

Patent

active

057109397

ABSTRACT:
A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with data communication rates which are controlled by the host and slave state machines in accordance with the commands from the command registers. The communications of control signals by the host and slave state machines are responsive to their control signals with such responsiveness being controllable in accordance with the commands from the command registers. The communication of data from the FIFO to the peripheral device is halted by the host state machine in accordance with its commands from the command registers. The command registers include a status register for storing data from the peripheral device representing a number of status states of the peripheral device.

REFERENCES:
patent: 3975712 (1976-08-01), Hepworth et al.
patent: 4644547 (1987-02-01), Vercellotti et al.
patent: 4933838 (1990-06-01), Elrod
patent: 5097410 (1992-03-01), Hester et al.
patent: 5189319 (1993-02-01), Fung et al.
patent: 5204953 (1993-04-01), Dixit
patent: 5254888 (1993-10-01), Lee et al.
patent: 5259006 (1993-11-01), Price et al.
patent: 5280584 (1994-01-01), Caesar et al.
patent: 5301275 (1994-04-01), Vanbuskirk et al.
patent: 5335329 (1994-08-01), Cox et al.
patent: 5404452 (1995-04-01), Detschel et al.
patent: 5404473 (1995-04-01), Papworth et al.
patent: 5408626 (1995-04-01), Dixit
patent: 5471638 (1995-11-01), Keeley
patent: 5481736 (1996-01-01), Schwartz et al.
patent: 5502826 (1996-03-01), Vassiliadis et al.
Serra, Micaela & Dervisoglu, Bulent I, "Testing", Chapter 79, The Electrical Engineering Handbook, Richard C. Dorf, Editor-in-Chief, pp. 1808-1837, CRC Press.
L-T Wang et al., "Feedback Shift Registers For Self-Testing Circuits", VLSI Systems Dsign, Dec. 1986.
Masakazu Shoji, "CMOS Dynamic Gates", Chapter 5, AT&T CMOS Digital Circuit Technology, Prentice Hall, 1988, pp.210-257.
Guthrie, Charles, "Power-On Sequencing For Liquid Crystal Displays; Why, When And How", Sharp Application Notes, Sharp Corporation, 1994, pp. 2-1 thru 2-9.
Bernd Moeschen, "NS32SP160--Feature Communication Controller Architecture Specification", National Semiconductor, Rev. 1.0, May 13, 1993.
Agarwal, Rakesh K., 80.times.86 Architecture and Programming, Vol. II: Architecture Reference, Chapter 4, Prentice Hall, 1991, pp. 542-543.
Intel486 Microprocessor Family Programmer's Reference Manual, Intel Corporation, 1993.
"8237A High Performance Programmable DMA Controller (8237A, 8237A-4, 8237A-5)", Peripheral Components, Intel, 1992, pp. 3-14 thru 3-50.
Kane, Gerry, "R2000 Processor Programming Model", Chapter 2, MIPS RISC Architecture, MIPS Computer Systems, Inc.
Hennessy, John, et al., "Interpreting Memory Addresses", Computer Architecture A Quantitative Approach, pp. 95-97, Morgan Kaufmann Publishers, Inc. 1990.
PowerPC601 Reference Manual, IBM, 1994, Chapter 9, "System Interface Operation", pp. 9-15 thru 9-17.
Intel Corp. Microsoft Corp., Advanced Power Management (APM) BIOS Interface Specification, Revision 1.1, Sep. 1993.
Intel Corporation, i486 Micro Processor Hardware Reference Manual, Processor Bus, pp. 3-28 thru 3-32.

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