Bidirectional FIFO with parity generator/checker

Details Bidirectional FIFO with parity generator/checker Bidirectional FIFO with parity generator/checker

1992-07-16

1994-09-20

Eng, David Y.

Boots, shoes, and leggings

3642443, 3649654, G06F 506

Patent

active

053496833

ABSTRACT:
A bidirectional first-in first-out buffer device including on a single chip a single bank FIFO memory array, two bidirectional input/output ports, an input multiplexer for selecting which port to input data from, an output multiplexer for selecting which port to output data to, a byte/word converter for converting input data from a byte format to a word format, a word/byte converter for converting output data from a word format to a byte format, a parity generator/checker for generating parity output signals or confirming parity input signals, a flag generator for generating empty/full and half full flags, and control logic for controlling the direction, format and timing of data flow. The device is packaged in a 52-pin plastic leaded chip carrier package.

REFERENCES:
patent: 4642794 (1987-02-01), Lavelle
patent: 4672646 (1987-06-01), Maren
patent: 4835418 (1989-05-01), Hsieh
patent: 4899307 (1990-02-01), Lenoski
patent: 5079693 (1992-01-01), Miller
patent: 5132987 (1992-07-01), Motohashi
patent: 5173619 (1992-12-01), Gaudenzi
patent: 5248908 (1993-09-01), Kimura
Cypress Semiconductor Preliminary CY7C439 data sheet.
Sharp LH5420 data sheet.

Affiliated with

Also associated with

Rating

Bidirectional FIFO with parity generator/checker does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bidirectional FIFO with parity generator/checker, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bidirectional FIFO with parity generator/checker will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2430606