Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached. A buffer counter indicating the amount of data in each FIFO is initialized at zero for outbound transfers from the workstation to the adapter or at the maximum buffer count for inbound transfers from the adapter to the workstation. The buffer count is incremented in response to accesses from the workstation side and is decremented in response to accesses from the adapter side, regardless of the direction of transfer.
patent: 3601809 (1971-08-01), Gray et al.
patent: 4062059 (1977-12-01), Suzuki et al.
patent: 4258418 (1981-03-01), Heath
patent: 4285038 (1981-08-01), Suzuki et al.
patent: 4454595 (1984-06-01), Cage
patent: 4607328 (1986-08-01), Furukawa et al.
patent: 4750107 (1988-06-01), Buggert
patent: 4809269 (1989-02-01), Gulick
patent: 4823312 (1989-04-01), Michael et al.
patent: 4839791 (1989-06-01), Ito
patent: 4847812 (1989-07-01), Lodhi
patent: 4866597 (1989-09-01), Kinoshita
patent: 4888727 (1989-12-01), Getson, Jr. et al.
patent: 4920480 (1990-04-01), Murakami et al.
patent: 4942515 (1990-07-01), Marzucco et al.
patent: 4942553 (1990-07-01), Dalrymple et al.
Akeley et al., "High-Performance Polygon Rendering", Aug. 1988, pp. 239-246.
IBM Technical Disclosure Bulletin, vol. 32, No. 9A, Feb. 1990, "Paralleling Links in a Unified Switching Architecture for Circuit/Packet Switching", pp. 45-49.
Research Disclosure, Feb. 1988, No. 28609, "Control of a Bi-Directional Data Cache Using a Single Buffer Counter".
Milot Paul J.
Spencer Jeffrey S.
Wilson Leslie R.
International Business Machines - Corporation
Kinnaman Jr. William A.
Richardson Robert L.
Walker Mark S.
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