Bidirectional electronic switch

Details Bidirectional electronic switch Bidirectional electronic switch

1999-04-21

2001-09-18

Huynh, Kim (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific quantity comparison means

C361S091100, C361S093900, C361S100000

Reexamination Certificate

active

06292341

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronics, and more particularly to the protection of devices and circuits of electronic control units from accidental current overloads.
BACKGROUND OF THE INVENTION
The use of central processing units (CPU) for controlling industrial processing equipment has become increasingly widespread. CPUs provide control in a more precise manner than possible with traditional automatic, mechanical and/or electromechanical controllers. These electronic control units generally also provide for a diagnostic interface of the operating conditions of the motor or of the device being controlled. These diagnostic functions require the presence of dedicated diagnostic output lines, to which may be coupled a suitable electronic testing apparatus.
A typical example of these types of applications is the electronic control unit of the engine of a car or of similar means of transportation. Thus, the ensuing description refers to a generic motor'electronic control unit (ECU) having one or more diagnostic output lines (K-lines) through which a tester may be coupled. These diagnostic lines may be useful to detect malfunctions and/or exploited to activate an alarm or antitheft system, such as, for example, a motor vehicle “immobilizer”.
A typical application scheme is shown in FIG.
1
. The engine's control unit, or simply the ECU, may be represented by a resistive load R
load
(current being absorbed by the control unit) and by a capacitive load C
load
(electrolytic capacitors of large value usually connected in parallel to the control unit). The diagnostic output interface is a K-line that may be represented by an interfacing DMOS transistor MI for motor vehicles. The characteristics of these diagnostic interfaces are defined by the standard ISO 9141. The tester is generally represented by an electrical model composed of a mechanical switch and a pull-up resistance Rp, as in FIG.
1
.
A serious problem arises if the ECU is accidentally disconnected from ground, due to a false contact or to any other cause. In this case, the only point at that instant that may be coupled to ground is the K-line output, through the switch (tester). An undue flow of the current absorbed by the ECU through such an output line must be averted in order to avoid damage to the interface device MI.
A simple approach to this problem is to place a diode in series to the K-line output, as illustrated in FIG.
2
. If, by any cause, a ground disconnection occurs, the diode is reverse biased so that the current cannot flow and thus the ECU is protected. The drawback of this known approach is the voltage drop on the guard diode which may reach about 1V during normal functioning conditions. Therefore the minimum voltage at the output of the diagnostic line K-line becomes: Vdiode+Vdmos. Under certain circumstances, this condition may jeopardize a correct recognition of a logic zero.
Another known approach is depicted in FIG.
3
. In this case, the diode is substituted by a guard DMOS transistor MP, the source of which is connected to the K-line output and the drain to the interface DMOS transistor MI that is used for communicating through the K-line. During normal operating conditions, the second guard DMOS transistor MP is turned on with a gate voltage, which in the illustrated example, is equal to R*I, through the comparator COMP of the output voltage VOUT, the logic AND gate A
1
, the controlled current generator I and the resistor R. The output voltage drop does not increase if the areas of the two power transistors MI and MP are properly dimensioned.
Should a below ground potential (negative potential) or a ground disconnection occur during normal functioning, the comparator COMP turns off the current generator I. The voltage present on the gate of the DMOS transistor MP decreases with a time constant &tgr;=RC
par,DMOS
, turning it off and impeding the passage of an inverse current through the interface DMOS transistor MI. In order to attain a low conduction resistance R
on
, the two DMOS transistors should have a large area of integration, but this implies relatively large parasitic capacitances (C
par,Mos
), on the order of tens of pF. By hypothesizing a parasitic capacitance of 100 pF, with R=10 K&OHgr;, the time constant will be &tgr;=1 &mgr;S. The complete switch-off of the DMOS transistor MP could occur after approximately 1.5&tgr;. During this interval, a large inverse current that may be of several amperes, flows through the DMOS transistor MP. This current is large because of a relatively low R
load
and because of a large C
load
that contributes to lower the impedance during the transients.
An approach to the problem could be reducing he resistance as much as possible, but this would markedly increase the bias current of the circuit that, in modern applications, is required to be lower and lower.
The following condition may also occur during normal functioning. The standard ISO 9141 considers that the diagnostic line K-line output may drop to −1V, as compared to the ground potential of the circuit.
During the switch-off transient, a portion of the inverse current comes from the substrate of the DMOS transistor MI, through the parasitic diode D
par
. It is important to limit this current in order to prevent problems in other areas of the integrated circuit that may be caused by substrate currents.
SUMMARY OF THE INVENTION
An efficient approach to the above cited problems and limitations of known circuits has been found. The invention achieves an almost complete elimination of the inverse current during the transient of a below ground occurrence or an accidental ground disconnection, while minimizing the bias current of the protection or guard circuit at the same time.
According to this invention, these benefits and advantages are attained by using an additional MOS transistor for switching off a second DMOS guard transistor, during a below ground condition. This allows a time constant of two orders of magnitude lower than that possible with the known circuits where the time constant is relatively high because of a value of the resistance R that cannot be lowered below a certain limit for other reasons.
The invention is directed to a protection circuit of a diagnostic output line (K-line) of a control unit for protection of the control unit in the event of a disconnection of the control unit circuits from ground or of a below ground condition. The diagnostic output line comprises a first interface DMOS transistor with a source connected to ground and a drain coupled to the diagnostic output line through a second DMOS transistor with a source connected to the diagnostic output line and a drain connected to the source of the first DMOS transistor.
Also, the protection circuit includes a comparator for the voltage of the diagnostic output line with the potential of the ground node of the circuits of the control unit, a two-input logic gate, having a first input connected to the output of the comparator and a second input coupled to the gate of the first DMOS transistor, whose output controls a current generator forcing a current, limited by a resistor, on the diagnostic output line. The gate of the second DMOS transistor is coupled to the connection node between the controlled current generator and the limiting resistor.
Furthermore, the protection circuit comprises a third MOS transistor for switching off the second DMOS transistor, functionally coupled in parallel to the resistor and controlled by a line comprising a second current generator controlled through an inverter by the output of the comparator and forcing a current through a voltage divider on the diagnostic output line. The intermediate node of the voltage divider is coupled to a gate of the third MOS transistor, and a third current generator is connected between the gate node of the third transistor and ground. The third MOS transistor is controlled by the output of the comparator in phase with the first current generator and in opposite phase from the second cu

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