Bidirectional drain to drain stacked FET gating circuit

Details Bidirectional drain to drain stacked FET gating circuit Bidirectional drain to drain stacked FET gating circuit

1982-09-28

1984-12-11

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307577, 307583, 307585, H03K 1708, H03K 1710, H03K 17687

Patent

active

044880685

ABSTRACT:
A bidirectional power FET circuit for AC application has a plurality of pairs of enhancement mode power FETs. Each pair has first and second power FETs connected drain to drain in series relation. The pairs are stacked in series between first and second main terminals. A plurality of gating circuits, one gating circuit for each power FET pair, are stacked in series for driving the power FET pairs sequentially into conduction from a single gate terminal.

REFERENCES:
patent: 3651342 (1972-03-01), Dingwall
patent: 3789244 (1974-01-01), Provanzano
patent: 4015146 (1977-03-01), Aihara et al.
patent: 4317055 (1982-02-01), Yoshida et al.
Grayeff et al., "FETs Provide Current Limiting for Protection Against Shorts", Electronic Design 12, p. 160, Jun. 7, 1976.

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