Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1991-08-05
1992-12-22
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307454, 307465, 36518901, 36518905, H03K 19177
Patent
active
051736195
ABSTRACT:
A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
REFERENCES:
patent: 2873363 (1959-02-01), Wanlass
patent: 2951951 (1960-09-01), Morgan
patent: 3112413 (1963-11-01), Zimbel
patent: 3170075 (1965-02-01), Mellott
patent: 3215852 (1965-11-01), Brode et al.
patent: 3231763 (1966-01-01), Mellott
patent: 3283175 (1966-11-01), Webb
patent: 3324307 (1967-06-01), Mellot et al.
patent: 3421026 (1969-07-01), Stopper
patent: 3424923 (1969-01-01), Mellot
patent: 3914628 (1975-10-01), Pao et al.
patent: 4031412 (1977-06-01), Ohhinato
patent: 4357547 (1982-11-01), Espe et al.
patent: 4528465 (1985-07-01), Harvey
patent: 4592023 (1986-05-01), Beranger et al.
patent: 4614884 (1986-09-01), Nagano
patent: 4707623 (1987-11-01), Bismarck
patent: 4746818 (1988-05-01), Hafner
patent: 4763303 (1988-08-01), Flannigan
patent: 4849935 (1989-07-01), Miyazawa
patent: 4975595 (1990-12-01), Roberts et al.
patent: 5017813 (1991-05-01), Galbraith et al.
patent: 5023484 (1991-06-01), Pathak et al.
Microelectronics: Digital & Analog Circuits and Systems 1979, p. 109, International Student Edition, McGraw-Hill, Inc., Singapore.
Gaudenzi Gene J.
Kramer Kevin G.
Tempest Susan L.
Brandt Jeffrey L.
Huberfeld Harold
International Business Machines - Corporation
Miller Stanley D.
Ouellette Scott A.
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