Bidirectional boundary-scan circuit

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G01R 3128

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052609480

ABSTRACT:
A boundary-scan circuit for a bidirectional pin of an integrated circuit which uses fewer standard cells if a cell design is considered, or fewer devices if non-standard cell integrated circuits are considered. In either case, the present invention provides the same functionality as provided in of the bidirectional boundary-scan circuits shown in TEEE 1149.1 in a circuit that should be more compact for the same logic family and integration technology.

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Gloster, et al., Boundary Scan with Built-In Self-Test, IEEE Design & Test of Computers, Feb. 1989, pp. 36-44.
C. W. Starke, An Efficient Self-Test Strategy for Testing VLSI-Chips, IEEE CH 2704-5/89/0000/5116/501.00, 1989, pp. 5-116 to 5-119.
IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Computer Society, Test Technology Technical Committee, IEEE Standard 1149.1-1989/D3.

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