BICMOS semiconductor integrated circuit device and...

Details BICMOS semiconductor integrated circuit device and... BICMOS semiconductor integrated circuit device and...

2002-09-10

2004-11-09

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S347000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000

Reexamination Certificate

active

06815822

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a BiCMOS (having both bipolar and CMOS) integrated circuit device and a fabrication process thereof. In particular, the invention relates to a BiCMOS device including both a CMOSFET region having an SOI (Silicon on Insulator) structure and a bipolar transistor region having a bulk structure, which device is used for LSI for high-speed optical network systems, or LSI for broadband wireless systems and is suited for high speed operation; and a fabrication process of the device.
2. Description of the Related Art
A BiCMOS device which has both an SOI structure region and a bulk structure region (free of an SOI layer) and has a MOS transistor formed in the SOI structure region and a vertical bipolar transistor in the bulk structure region is described in FIG. 4 on page 1382 of “IEEE Transaction on Electron Devices, Vol. 41, No. 8, pp1379 to 1387(1994)” (which will be hereinafter called “first prior art”).
This first prior art is characterized in that selective epitaxial growth (SEG) and planarizing polishing are conducted, each twice. By the first selective epitaxial growth and first planarizing polishing, the collector region of the bipolar transistor and i-type bulk substrate region for the SOI structure are formed. An n
+
type collector region is formed by selective diffusion of high-concentration impurities into this collector region. By the second selective epitaxial growth and second planarizing polishing, the n
−
type collector region of the bipolar transistor and an SOI region are formed. By the formation of p type base region and n type emitter region in this n
−
type collector region, an npn bipolar transistor is formed, while MOSFET is formed in the SOI region.
In addition, a BICMOS technique using an SOI region is disclosed, for example, in U.S. Pat. No. 5,484,738 (second prior art), Japanese Patent Application Laid-Open No. Hei 6-310665 (third prior art), or Japanese Patent Application Laid-Open No. Hei 7-99259 (fourth prior art), while an IC device using SOI is disclosed, for example, in U.S. Pat. No. 5,399,507 (fifth prior art) or U.S. Pat. No. 4,908,328 (sixth prior art). Among them, in the third, fourth and fifth prior arts, a so called SIMOX (separation by implantation of oxygen) technique of forming an SOI region by oxygen ion implantation inside of a semiconductor substrate is employed.
A schematic longitudinal cross-sectional view of the BiCMOS device which was investigated on trial by the present inventors based on the first prior art is shown in FIG.
7
. In this diagram, only an npn type vertical bipolar transistor and an n channel insulated gate type transistor (which will hereinafter be called “MOS transistor”) are illustrated and a p channel MOS transistor is omitted. In addition, not closely related portions upon comparison with the invention product are omitted.
In
FIG. 7
, indicated at reference numeral
1
is a p type Si substrate,
2
an SiO
2
layer,
3
a p type SOI layer,
4
an n
+
type Si layer,
5
a low-doped n
−
type Si layer,
61
,
7
, each an SiO
2
film,
8
an n
+
type Si layer,
9
an SiO
2
film,
10
an n
+
type polycrystalline Si film,
11
an SiO
2
film,
12
an n
+
type SOI layer,
15
a P
+
type polycrystalline Si film,
16
,
17
, each an SiO
2
film,
18
a p type Si layer,
181
a P
+
type Si layer,
20
an n
+
type polycrystalline Si film,
21
an n
+
type Si layer,
23
an SiO
2
film,
24
a metal plug, and
25
to
29
, each a metal film. Indicated at reference numeral
4
is a buried n
+
type collector layer for the collector,
5
a low-doped n
−
type collector layer,
18
a base layer, and
21
an emitter diffusion layer of a bipolar transistor. Reference numeral
12
indicates source/drain diffusion layers of an MOS transistor. Among the metal electrodes, that indicated at reference numeral
25
serves as a base electrode,
26
an emitter electrode and
27
a collector electrode of the bipolar transistor, and
28
a source electrode and
29
a drain electrode of the MOS transistor.
The buried collector layer
4
of a bipolar transistor is formed at an equal surface level to the bulk substrate (SOI-layer supporting substrate) of an SOI structure. In other words, the upper surface of the buried collector layer
4
, that is, the lower portion (which will also be called “lower surface” or “bottom portion”) of the low-doped collector layer
5
is at a substantially equal level to the lower portion (lower surface or bottom surface) of the buried silicon oxide layer (BOX layer)
2
. Here, the boundary between the buried collector layer
4
and the low-doped collector layer
5
is defined as to located at a position having an impurity concentration by about one figure lower than the peak of the impurity concentration of the buried collector layer
4
, for example, a position having an impurity concentration of 3×10
18
cm
−3
. The height level of the surface of the Si substrate in the bulk structure region (that is, the surfaces of the emitter layer
21
and base lead-out layer
181
) is at an equal level to the upper surface of the SOI layer
3
and thus, the whole substrate surface is planarized. In this bulk structure region, the low-doped collector layer
5
, base layer
18
, base lead-out layer
181
and emitter layer
21
of a bipolar transistor are disposed in the height level between the lower portion (lower surface, bottom surface) of the BOX layer
2
and the upper surface of the SOI layer
3
.
FIG. 9
schematically illustrates the positional relationship, in the investigated example illustrated in
FIG. 7
, among the surface of the SOI layer (its height position is indicated at letter A), the surface of the bulk structure region (B), the lower surface of the BOX layer (C) and the upper surface (D) and lower surface (E) of the low-doped collector layer of the bipolar transistor and the height position A of the surface of the SOI layer is equal to the height position B of the surface of the bulk structure region, while the height position E of the lower surface of the low-doped collector layer is substantially equal to the height position C of the lower surface of the BOX layer. Accordingly, the difference (B−E) between the height position B of the surface of the bulk structure region and the height position E of the lower surface of the low-doped collector layer is substantially equal to the total thickness (A−C) of the SOI layer and BOX layer. In this example, (A−C) is set at 0.5 &mgr;m (micrometer) and the depth of the base diffusion layer is set at about 0.1 &mgr;m (micrometer), resulting in the thickness (D−E) of the low-doped collector layer of about 0.4 &mgr;m (micrometer).
Another process for fabricating the integrated circuit device structure as illustrated in
FIG. 7
or
FIG. 9
is proposed. Described specifically, this process comprises disposing a BOX layer and an SOI layer over the principal surface of a Si semiconductor substrate in advance (preparing an SOI wafer), partially removing the SOI layer and BOX layer from a region wherein a bipolar transistor is to be formed, forming an n
+
type collector layer over the surface of the bulk Si substrate by ion implantation or heat diffusion, thereby forming a buried collector layer
4
, subjecting non-doped or n
−
type Si single crystals to selective epitaxial growth with the n
+
type collector layer as a seed, shaving the surface of the Si single crystals in the bulk structure region by polishing to make its height equal to the surface height of the SOI layer and then forming base and emitter layers on the surface of the bulk structure region. This process is convenient for mass production because a thin SOI layer is formed in advance so that its thickness or properties can be controlled easily.
In order to attain speed increase and reduction in a power consumption amount of the MOS transistor on the SOI layer, it is desired to form

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