BiCMOS process with surface channel PMOS transistor

Details BiCMOS process with surface channel PMOS transistor BiCMOS process with surface channel PMOS transistor

1994-07-27

1996-04-09

Wojciechowicz, Edward

Fishing, trapping, and vermin destroying

437 46, 437 47, 437 60, 437109, 437200, 437233, 437918, 437913, 437933, 257370, 257379, 257384, 257408, 257412, H01L 21265, H01L 2976

Patent

active

055061583

ABSTRACT:
A BiCMOS device 10 having a bipolar transistor 60, a PMOS transistor 64 and a p-type polysilicon resistor 70. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. PMOS transistor 64 comprises source/drain regions 52, gate electrode 40, and gate oxide 28. PMOS transistor 64 may also comprises LDD regions 44. The emitter electrode 30 and gates 40 are formed out of the same polysilicon layer and thus have the same thickness. If desired, the emitter electrode 30 and gate electrodes 40 may be silicided.

REFERENCES:
patent: 5107321 (1992-04-01), Ilderem et al.

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