BiCMOS process for supporting merged devices

Details BiCMOS process for supporting merged devices BiCMOS process for supporting merged devices

1993-12-03

1995-08-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 59, 437200, 148DIG9, H01L 218248

Patent

active

054419034

ABSTRACT:
A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

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H. Momose, T. Maeda, K. Inoue, I Kamohara, T. Kobayashi, Y. Urakawa, and K. Maeguchi, "Characterization of Speed and Stability fo BiNMOS Gates with a Bipolar and PMOSFET Merged Structure", Dec. 9-12, 1990, International Electron Devices Meeting, pp. 231-234.
H. Momose, T. Maeda, K. Inoue, Y. Urakawa and K. Maeguchi, "Novel Test Structures for the Characterization of Latch-Up Tolerance in a Bipolar and MOSFET Merged Device", Proc. IEEE 1991 Int. Conference on Microelectronic Test Structures, vol. 4, No. 1, Mar. 1991, pp. 225-230.
Ghandhi, "VLSI Fabrication Principles", pp. 321-329, 1983.

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