BICMOS process for forming shallow NPN emitters and mosfet sourc

Details BICMOS process for forming shallow NPN emitters and mosfet sourc BICMOS process for forming shallow NPN emitters and mosfet sourc

1989-10-03

1991-10-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 31, 437 40, 437 56, 437 57, 437 59, 437189, 437196, 437200, 148DIG9, H01L 21283

Patent

active

050595466

ABSTRACT:
A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the steps of first forming bipolar and MOS regions and then patterning gate electrodes in the MOS regions to define source/drain regions on either side thereof. A layer of oxide is formed over the bipolar transistor region which has an intrinsic base defined therein. The oxide is patterned to form an opening for an emitter and an opening for an extrinsic base, the opening separated by a layer of oxide. The refractory metal is then sputtered over the substrate and a silicide layer forms in the emitter and base regions of the bipolar transistor and the source/drain regions of the MOS transistors. The silicided layers are implanted with the refractory metal layer forming a mask on the sidewalls of the gate electrode of the MOS transistors and the portion of the refractory metal layer over the spacing oxide between the emitter and the base regions to mask the implanted impurities from the region in the silicon therebelow to provide a self-aligned process. The unreacted refractory metal is then removed and the impurities driven down to the substrate to define a metallurgical junction below the silicided layers.

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