BICMOS output interface circuit for level-shifting ECL to CMOS

Details BICMOS output interface circuit for level-shifting ECL to CMOS BICMOS output interface circuit for level-shifting ECL to CMOS

1988-06-03

1989-07-18

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307446, 307557, 307246, H03K 1901

Patent

active

048496600

ABSTRACT:
An output interface circuit comprises a CMOS circuit including a pair of complementary MOS transistors and receiving an input signal at the gates of the paired MOS transistors, a bipolar transistor having its base connected to the output of the CMOS circuit and its emitter from which an output signal is delivered, and a control circuit connected between the paired MOS transistors and operable, upon the fall of the output signal, to cut off a current flowing through any one of the paired MOS transistors so as to control the low level at the output of the CMOS circuit such that the low level does not fall before a potential level by which the low level of the output signal is permitted to be at a desirable predetermined potential level. Specifically, the CMOS circuit includes a pair of complementary MOS transistors comprised of a P-type MOS transistor and an N-type MOS transistor and receives an input signal of CMOS level to operate in inverter fashion. The bipolar transistor connected to the output of the CMOS circuit operates as an emitter follower to deliver an output signal of ECL level. Upon the fall of the output signal, the control circuit operates to cut off a current flowing through the N-type MOS transistor so as to control the low level at the output of the CMOS circuit such that the low level does not fall below a level which is about 0.5 to 0.8 volts higher than the low level of the output signal (ECL level) of the bipolar transistor.

REFERENCES:
patent: 3649843 (1972-03-01), Redwine et al.
patent: 4366397 (1982-12-01), Kitamura et al.
patent: 4645951 (1987-02-01), Uragami
patent: 4646124 (1987-02-01), Zunino
patent: 4656372 (1987-04-01), Sani et al.
patent: 4740713 (1988-04-01), Sakurai et al.
patent: 4751410 (1988-06-01), Tanizawa
patent: 4782251 (1988-11-01), Tsugaru et al.
patent: 4794317 (1988-12-01), van Tran
patent: 4798981 (1989-01-01), Tsugaru et al.
patent: 4798983 (1989-01-01), Mori
"TTL Level High Speed BIFET Receiver", IBM T.D.B., vol. 30, No. 8, Jan. 1988, pp. 394-395.
Hudson et al., "An ECL Compatible 4K CMOS RAM", ISSCC '82 Digest of Technical Papers, pp. 248-249.

Affiliated with

Also associated with

Rating

BICMOS output interface circuit for level-shifting ECL to CMOS does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with BICMOS output interface circuit for level-shifting ECL to CMOS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and BICMOS output interface circuit for level-shifting ECL to CMOS will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-174418