BiCMOS noninverting buffer and logic gates

Details BiCMOS noninverting buffer and logic gates BiCMOS noninverting buffer and logic gates

1990-06-19

1991-09-17

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, H03K 1902, H03K 1908

Patent

active

050497650

ABSTRACT:
A BiCMOS logic circuit which implements single stage noninverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and output nodes. The pull-down assemby means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration drives the base of a bipolar transistor coupled to the output node.

REFERENCES:
patent: 4425516 (1984-01-01), Wanlass
patent: 4636665 (1987-01-01), McLaughlin
patent: 4678943 (1987-07-01), Uragami et al.
patent: 4701642 (1987-10-01), Pricer
patent: 4703203 (1987-10-01), Gallup et al.
patent: 4779014 (1988-10-01), Masuoka et al.
patent: 4808850 (1989-02-01), Masuda et al.
patent: 4827159 (1989-05-01), Naganuma
patent: 4837462 (1989-06-01), Watanabe et al.
patent: 4845385 (1989-07-01), Ruth, Jr.
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 4871928 (1989-10-01), Bushey
A. R. Alvarez, BiCMOS Technology and Applications, pp. 1-5; 165-175; and 182-186 (1989).

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