BICMOS NAND gate

Details BICMOS NAND gate BICMOS NAND gate

1988-05-23

1989-09-12

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307451, 307570, H03K 1716, H03K 1902, H03K 19094

Patent

active

048663042

ABSTRACT:
A BICMOS NAND gate has P channel transistors, N channel transistors, and NPN transistors. The NPN transistors and the P channel transistors combine to provide logic high drive which avoids having the comparatively slow P channel transistors tied together. The P channel transistors are combined with NPN transistors to avoid the accumulation of capacitance that must be driven by a P channel transistor as the number of inputs increases. This avoids the typical problem of having the P channel transistors having to drive more capacitance as the number of inputs increases.

REFERENCES:
patent: 4694202 (1987-09-01), Iwamura et al.
patent: 4730132 (1988-03-01), Watanabe et al.

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