BICMOS logic gate with higher pull-up voltage

Details BICMOS logic gate with higher pull-up voltage BICMOS logic gate with higher pull-up voltage

1989-12-05

1991-03-12

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307446, H03K 1704

Patent

active

049995235

ABSTRACT:
A novel BICMOS output buffer is taught including circuit means for firstly discharging the bases of the bipolar pull up and bipolar pull down transistors, and secondly to connect the base of an output transistor to its emitter when that output transistor is conducting, thereby insuring maximum voltage swing of the output voltage. The circuit means comprises an MOS transistor for discharging the base of an output transistor, and a depletion mode MOS transistor for connecting the base of an output transistor to its emitter. By utilizing MOS and depletion mode transistors, a significant area advantage is achieved, particularly when the MOS and depletion mode transistors are merged.

REFERENCES:
patent: 4103188 (1978-07-01), Morton
patent: 4301383 (1981-11-01), Taylor
patent: 4612458 (1986-09-01), Vasseghi et al.
patent: 4682054 (1987-07-01), McLaughlin
patent: 4746817 (1988-05-01), Banker et al.
patent: 4791320 (1988-12-01), Kawata et al.
patent: 4816705 (1989-03-01), Ohba et al.
patent: 4845385 (1989-07-01), Ruth, Jr.
patent: 4883979 (1989-11-01), Tran
patent: 4948994 (1990-08-01), Akioka et al.
Cham et al., "Computer-Aided Design And VLSI Device Development", Second Edition Kluwer Academic Publishers, pp. 326-330.
"Optimization and Scaling of CMOS-Bipolar Drivers for VLSI Interconnects", by De Los Santos, IEEE Transactions on Electron Devices, vol. ED-33, No. 11 (1986).
"A BICMOS Logic Gate with Positive Feedback", Nishio et al., IEEE International Solid State Circuits Conference (1989).
"0.5 Micron BICMOS Technology", by H. Momose et al., Circuit Technology R & D, Hewlett Packard Company, IEEE IEDM (1987).
"A New Device Interconnect Scheme for Sub-Micron VLSI", by Chen et al., Hewlett Packard Laboratories, IEDM (1984).

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