BiCMOS logic gate having plural linearly operated load FETs

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307443, 307455, 3072966, H03K 1716

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active

052834794

ABSTRACT:
An improved BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal providing a variable load resistance. The control signal is preferably provided by a feedback network which maintains a constant voltage swing across the network over temperature.

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"BiCMOS Technology and Applications", edited by Antonio R. Alvarez, Kluwer Academic Publishers, 1990, Chapter 5 (pp. 165-200).

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