BICMOS logic gate

Details BICMOS logic gate BICMOS logic gate

1992-04-30

1993-10-12

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072966, 3072968, 307570, H03K 1902

Patent

active

052528626

ABSTRACT:
A BICMOS NAND gate (40) has a CMOS NAND gate (41), a bipolar pull-up transistor (47), a bipolar pull-down transistor (48), series connected N-channel transistors (43-45) coupled between the base and collector of pull-down transistor (48), N-channel transistors (42, 46, 49, and 50), and a V.sub.BG generated reference voltage (51). N-channel transistor (46) receives a variable bias voltage provided by transistors 49, 50, and V.sub.BG generated reference voltage (51). At high power supply voltages, N-channel transistor (46) prevents pull-down transistor (48) from becoming saturated when BICMOS NAND gate (40) is operating at high frequency, when an input becomes skewed, or a glitch develops, yet allows for satisfactory operation BICMOS NAND gate (40) at low power supply voltages.

REFERENCES:
patent: 4595844 (1986-06-01), Shen
patent: 4616146 (1986-10-01), Lee et al.
patent: 4929853 (1990-05-01), Kim et al.
patent: 5027009 (1991-06-01), Urakawa et al.
patent: 5155392 (1992-10-01), Nogle

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