Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1991-03-25
1992-05-12
Hudspeth, David
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307475, 307455, H03K 1902, H03K 190175
Patent
active
051130955
ABSTRACT:
A logic circuit for receiving both CMOS- and CML-level input voltages in one embodiment performs a logical OR function. A reference bipolar transistor is coupled to a first power supply voltage terminal through a first resistor. A second bipolar transistor for receiving a CML-level input signal is coupled to the first power supply voltage terminal through a second resistor. Emitters of the bipolar transistors are connected together. A MOS transistor for receiving a CMOS-level input signal has a drain connected to a collector of the second bipolar transistor, and a voltage dropping portion seperate the source of the MOS transistor from the emitters of the reference transistor and the bipolar transistor. The input voltages control a constant current conducted from a current source connected to the source of the MOS transistor. The logic circuit base-to-emitter reverse bias caused by CMOS logic levels.
REFERENCES:
patent: 4546272 (1985-10-01), Suzuki et al.
patent: 4800303 (1989-01-01), Graham et al.
patent: 4918640 (1990-04-01), Heimsch et al.
patent: 4939478 (1990-07-01), Heimsch et al.
patent: 5001370 (1991-03-01), Phan et al.
"Hot-Carrier Degradation in Bipolar Transistors at 300 and 110K--Effect on BiCMOS Inverter Performance", IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990, pp. 1171-1173.
Motorola MECL System Design Handbook, No. HB205R1, pp. 10-11.
Hudspeth David
Motorola Inc.
Polansky Paul J.
Sanders Andrew
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