BiCMOS logic circuit using 0.5 micron technology and having an o

Details BiCMOS logic circuit using 0.5 micron technology and having an o BiCMOS logic circuit using 0.5 micron technology and having an o

1990-10-29

1992-04-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307570, 307576, H03K 19094, H03K 1716

Patent

active

051071410

ABSTRACT:
An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.

REFERENCES:
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patent: 4880998 (1989-11-01), Ueda
patent: 4890017 (1989-12-01), Masuda et al.
"0.5 Micron BiCMOS Technology", Momose et al., Circuit Technology R & D Hewlett-Packard Company, 1987 IEEE.
K. Momose et al., "0.5 Micron BICMOS Technology", 1987 IEDM (IEEE-Int'l Electron Devices Meeting), pp. 838-840.
A. Watanabe et al., "Future BiCMOS Technology for Scaled Supply Voltage", 1989.
IEDM (IEEE-Int'l Electron Devices Meeting), pp. 429-432, Dec. 3-6, 1989.
H. Shin et al., "Full-Swing Complementary BiCMOS Logic Circuits", (Proc. 1989 IEEE Bipolar Circuits and Technology Meeting, Sep. 1989), pp. 229-232.
K. Natori et al., "A 34ns 256K DRAM", 1983 IEEE--Int'l Solid State Circuit Conf., Dig. of Technical Papers, pp. 232-233, 2/25/1983.
K. Itoh et al., "An Experimental 1Mb DRAM with On-Chip Voltage Limiter", 1984 IEEE-ISSCC (Dig. of Tech. Papers), pp. 282-283, 2/24/1984.
S. Kohyama et al., "Directions in CMOS Technology", 1983 IEDM (IEEE-Int'l Electron Devices Meeting), pp. 151-154.

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