BICMOS local address transition detection circuit

Details BICMOS local address transition detection circuit BICMOS local address transition detection circuit

1992-07-27

1993-11-30

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 307355, G11C 800

Patent

active

052672166

ABSTRACT:
A plurality of local address transition detector (LATD) circuits, one per address bit signal (Ai), of the type used in SRAMs to generate an on-chip clock pulse (LATDSi) that insures a correct timing of internal circuits such as sense amplifiers and address decoders that are essential for a correct READ/WRITE operation of the SRAM. According to one aspect of the invention, each LATD circuit includes: a first bipolar transistor (T1) serially connected with a first FET device (N1) forming a first branch; a second bipolar transistor (T2) serially connected with a second FET device (N2) forming a second branch. The first and second branches are connected in parallel between a first supply voltage (Vcc) and a common output node (N) connected to a circuit output terminal (30-i) where the output signal (LATDSi) generated by the LATD circuit (22-i) is available. The first and second bipolar transistors (T1, T2) are respectively driven by the address signal (Ai') and its complement (Ai') at the ECL voltage levels and the second and first FET devices are respectively driven by the address signal (Ai*' ) and its complement (Ai*') at the CMOS voltage levels. As a result of this design of the LATD circuit, the delays in critical paths in BICMOS circuits incorporating the LATD circuit may be significantly reduced relative to BICMOS circuits utilizing conventional LATD circuits.

REFERENCES:
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patent: 4749880 (1988-06-01), Kobatake
patent: 4897820 (1990-01-01), Shiomi et al.
patent: 4922122 (1990-05-01), Dubujet
patent: 5003513 (1991-03-01), Porter
"Two 13-ns 64K CMOS SRAM's with Very Low Active Powder and Improved Asynchronous Circuit Techniques," S. T. Flannagan et al., IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 692-703.
"A 6-ns 256-Kbit BICMOS TTL Sram," T. Akioka et al., IEEE 1990 Custom Integrated Circuits Conf., Boston Mass., pp. 24.3.1-24.3.4.
"An 8-ns 1-Mbit ECL BiCMOS SRAM with Double-Latch ECL-to-CMOS-Level Converters," M. Matsui et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1226-1231.

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