BICMOS level converter circuit

Details BICMOS level converter circuit BICMOS level converter circuit

1992-09-28

1994-05-24

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307300, H03K 19082, H03K 1920

Patent

active

053151798

ABSTRACT:
A BICMOS level converter (60) for use at lower power supply voltages includes an input buffer (20) for receiving an ECL level input signal and providing level shifted buffered signals referenced to V.sub.SS, a differential amplifier (61), a clamping circuit (71 and 72) for preventing the bipolar transistors (64 and 65) from operating in saturation, cross-coupled pull-up circuit (67) for a stronger transition from a logic low to a logic high, and a cross-coupled half-latch (75) for reducing the power consumption. The BICMOS level converter (60) has improved switching speeds, wider margins, and reduced power consumption for use at 3.3 volts.

REFERENCES:
patent: 4806799 (1989-02-01), Pelley, III et al.
patent: 4849659 (1989-07-01), West
patent: 4864159 (1989-09-01), Cornelissen
patent: 4988898 (1991-01-01), Jansson
patent: 4992681 (1991-02-01), Urakawa
patent: 5012137 (1991-04-01), Muellner
patent: 5059829 (1991-10-01), Flannagan et al.
patent: 5068551 (1991-11-01), Bosnyak
patent: 5148059 (1992-09-01), Chen
patent: 5148061 (1992-09-01), Hsueh
patent: 5216298 (1993-06-01), Ohba

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