BiCMOS latches with NPN control devices for current limiting...

Details BiCMOS latches with NPN control devices for current limiting... BiCMOS latches with NPN control devices for current limiting...

2003-06-06

2004-12-14

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

Reexamination Certificate

active

06831579

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic latches.
2. Description of the Related Art
A variety of modern signal-conditioning systems require electronic latches which can be latched to indicate the state of a fluctuating input signal at a selected latch time. Because these systems often process complementary metal-oxide-semiconductor (CMOS) signals and generally operate at high speeds, there is a continuing search for latch structures that enhance latch speed but provide CMOS-level latch signals.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to latch structures and systems that realize enhanced latch speed while providing CMOS-level latch signals. These goals are realized with bipolar junction structures and CMOS structures that are arranged to enhance regenerative feedback signals and generate CMOS-level latch signals.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 5625308 (1997-04-01), Matsumoto et al.
patent: 5760626 (1998-06-01), Pelley, III
patent: 5801565 (1998-09-01), Kuo
patent: 5808514 (1998-09-01), Kolluri
patent: 5825256 (1998-10-01), Tchamov et al.

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