BiCMOS-integrated photodetecting semiconductor device having...

Details BiCMOS-integrated photodetecting semiconductor device having... BiCMOS-integrated photodetecting semiconductor device having...

2000-07-28

2002-05-21

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S446000, C257S186000

Reexamination Certificate

active

06392282

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a BiCMOS-integrated: photodetecting semiconductor device and an avalanche photodiode (referred as APD) applicable to such a semiconductor device; and, in particular, to a BiCMOS-integrated photodetecting semiconductor device comprising a vertical type PNP transistor (referred as vertical type PNP-Tr), a MOS transistor, and an APD having a high sensitivity over ultraviolet, visible, and near-infrared regions, and an avalanche photodiode applicable to such a semiconductor device.
2. Related Background Art
Conventionally, most of APDs have been formed as single devices. In order to process optical signals received by an APD, the APD has been used together with signal processing integrated circuits or assembled into the same package with a signal processing semiconductor device so as to be used as a hybrid integrated circuit (hybrid IC).
On the other hand, Japanese Patent Application Laid-Open No. 2-218160 proposes an example of forming CCDs or MOS transistors and an APD. In this example, active elements such as transistors and an APD are constructed monolithically in one image sensor.
SUMMARY OF THE INVENTION
In the case where an APD is formed monolithically, since the APD is used for higher speed applications in general, a signal processing circuit for the APD necessitates wide-band electronic elements allowing the high speed operation thereof. Candidates for such electronic elements can be high-speed NPN transistors (referred as NPN-Tr) and PNP transistors (referred as PNP-Tr). One of NPN transistors, a vertical structure NPN-Tr suitable for high-speed operation, can easily be formed. Since the PNP-Tr, however, takes a lateral structure that is parasitically formed in the process of making the NPN-Tr, the performance of the PNP-Tr shows low speed and narrow-band.
However, since the APD and the signal processing circuit are assembled into the same package to form a hybrid IC, the configuration of the assembled hybrid IC is complicated. In the hybrid IC, electronic noise is likely to occur due to induction, and parasitic capacitance increases. Furthermore, it is difficult to arrange an array of APDs together with signal processing circuits therefor.
Japanese Patent Application Laid-Open No. 2-218160 publication discloses an example that necessitates complicated manufacturing steps, such as selective epitaxial growth, to form an APD, whereby the performance of the APD may not be sufficient, and it may be difficult to manufacture the APD in good yield. Also, since the NPN transistor in this publication is a parasitic transistor, it has high parasitic resistance such as emitter resistance, collector resistance, and/or base resistance. As a consequence, the performance, such as the linearity and frequency characteristics, of the transistor is not always sufficient to process signals from the APD. In other words, for manufacturing a high-performance APD capable of detecting weak high-speed optical signals, there is severe restriction concerning one manufacturing condition under which the PN junction of the APD should be formed, whereby its characteristics depend on the structure of the APD. On the other hand, in an integrated circuit formed of electronic elements, such as bipolar transistors and MOS transistors, there. is restriction concerning another manufacturing condition for integrating these elements. Hence, it is difficult to form both of them on the same substrate while exhibiting their respective characteristics.
In forming a bipolar transistor, on the other hand, an epitaxial layer is grown on a substrate. Although an epitaxial layer used for the bipolar transistor is relatively thin, an epitaxial layer used for the APD is relatively thick in order to attain a high sensitivity extending to the near infrared region. It is also difficult to satisfy these demands from both the APD and the bipolar transistor at the same time.
If a vertical type PNP-Tr is available in addition to a vertical type NPN-Tr as an electronic element used in a signal processing circuit for the APD, this allows the design of a complementary circuit capable of its high-speed operation. For constructing the vertical NPN-Tr, it is preferable to use a P-type substrate. The vertical PNP-Tr must be, therefore, constructed on the same P-type substrate. However, the collector of the vertical PNP-Tr cannot be isolated from the substrate in the P-type substrate, whereby the collector is always grounded. Consequently, the PNP-Tr suitable for the signal processing circuit cannot be obtained.
It is an object of the present invention to provide a BiCMOS-integrated photodetecting semiconductor device in which a vertical PNP-Tr and an APD can be constructed on the same P-type semiconductor substrate without decreasing their performance; and an APD applicable to this semiconductor device.
Therefore, the present invention is configured as follows:
The BiCMOS-integrated photodetecting semiconductor device in accordance with the present invention comprises: N-type first buried regions
3
formed in an upper surface portion of a P-type semiconductor substrate
1
in an avalanche photodiode forming area (referred as an APD forming area) and a vertical type PNP transistor forming area (referred as a vertical type PNP-Tr forming area); a P-type first semiconductor layer
5
formed on the P-type semiconductor substrate
1
and N-type first buried regions
3
in the APD forming area, the vertical type PNP-Tr forming area, P-channel MOS transistor forming area (referred as a PMOS-Tr forming area), an N-channel MOS transistor forming area (referred as an NMOS-Tr forming area), and a vertical type NPN transistor forming area (referred as vertical type NPN-Tr forming area); N-type second buried regions
7
formed in an upper surface portion of the P-type first semiconductor layer
5
in the PMOS forming area and NPN-Tr forming area; a P-type first buried region
9
formed in the upper surface portion of the P-type first semiconductor layer
5
on the N-type first buried region
3
in the vertical type PNP-Tr forming area; a P-type second buried region
11
formed, above the N-type first buried region
3
in the APD forming area, in the upper surface portion of the P-type first semiconductor layer
5
; a P-type second semiconductor layer
13
formed on the P-type first semiconductor layer
5
, P-type first buried region
9
, P-type second buried region
11
, and N-type second buried regions
7
; an N-type first semiconductor region
15
formed in contact with the N-type second buried region
7
in the vertical type NPN-Tr forming area; an N-type second semiconductor region
17
formed in contact with the N-type second buried region
7
in the PMOS-Tr forming area; an N-type third semiconductor region
19
formed on the P-type first buried region
9
in the vertical type PNP-Tr forming area; an P-type third semiconductor region
27
formed in an upper surface portion of the N-type first semiconductor region
15
in the vertical type NPN-Tr forming area; a N-type fourth semiconductor region
25
formed in the upper surface portion of the P-type third semiconductor region
27
in the vertical type NPN-Tr forming area so as to surround a bottom surface and a side surface of the N-type fourth semiconductor region
25
; and a P-type fourth semiconductor region
29
formed in an upper surface portion of the N-type third semiconductor region
19
in the vertical type PNP-Tr forming area; wherein the vertical type PNP-Tr is constituted such that the P-type first buried region
9
, P-type first semiconductor layer
5
, and P-type second semiconductor layer
13
in the vertical type PNP-Tr forming area form a collector thereof, the N-type third semiconductor region
19
forms a base thereof, and the P-type fourth semiconductor region
29
forms an emitter thereof; wherein the vertical type NPN-Tr is constituted such that the N-type second buried region
7
and N-type first semiconductor region
15
in the vertical type NPN-Tr forming area form a collector the

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