BICMOS input buffer circuit with integral passgate

Details BICMOS input buffer circuit with integral passgate BICMOS input buffer circuit with integral passgate

1992-06-12

1994-02-22

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307475, H03K 1704

Patent

active

052890562

ABSTRACT:
A BICMOS input buffer circuit (20) incorporates an integral CMOS passgate circuit (P2,N2) between bipolar input (Q1) and output (Q3,Q4,Q5) transistors of the input buffer circuit. Latch enable inputs (LE) receive latch enable signals for operating the input buffer circuit and internal passgate in a transparent mode for passing data signals from the input (V.sub.IN) to the output (V.sub.OUT) and in a blocking mode for blocking data signals. The internal CMOS passgate circuit (P2,N2) is coupled into the input buffer circuit (20) to control nodes of the transistor output pullup (Q4,Q5) and pulldown (Q3) for controlling the conducting states of the respective transistor output pullup and pulldown to implement the blocking and transparent modes. A third passgate transistor (P3) may also be coupled between a control node (m1) of the transistor output pullup (Q4,Q5) and the low potential power rail (GND) for positive turn off of the output pullup. A dynamic power enhancement circuit (DPC) provides transient enhancement for the transition from the blocking mode to transparent mode.

REFERENCES:
patent: 5006732 (1991-04-01), Nakamura
patent: 5051623 (1991-09-01), Yarbrough et al.
patent: 5070201 (1991-12-01), Ten Eyck
patent: 5107142 (1992-04-01), Bhamidipaty

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