BiCMOS input buffer circuit operable at high speed under less po

Details BiCMOS input buffer circuit operable at high speed under less po BiCMOS input buffer circuit operable at high speed under less po

1991-12-05

1993-07-06

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307570, 307443, H03K 1902, H03K 1920

Patent

active

052257177

ABSTRACT:
An input buffer circuit applicable as a BiCMOS RAM address buffer is disclosed. An improved level shift circuit 59 includes PMOS transistors 14 and 17 for bypassing emitter follower transistors 12 and 15, and NMOS transistors 13 and 16 for constituting a controllable current source Two differential amplifier circuits operating in response to an input signal having an ECL logic amplitude are provided, and emitter follower transistors 12 and 15 are driven by one of them, MOS transistors 13, 14, 16, and 17 are driven by the other. High operating speed is achieved under less current consumption, since emitter follower transistors 12 and 15, and MOS transistors 13, 14, 16, and 17 are driven, respectively.

REFERENCES:
patent: 4813020 (1989-03-01), Iwamura et al.
patent: 4868421 (1989-09-01), Herndon et al.
patent: 5065050 (1991-11-01), Fernandez
patent: 5140190 (1992-08-01), You et al.
"An 8 ns 256K BiCMOS RAM" (1988 IEEE International Solid State Circuits Conference, Digest of Technical Papers, pp. 184-185).

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