BiCMOS gate pull-down circuit

Details BiCMOS gate pull-down circuit BiCMOS gate pull-down circuit

1991-06-13

1992-06-02

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307570, 307300, 307443, H03K 1902, H03K 333

Patent

active

051189720

ABSTRACT:
BiCMOS gate pull-down circuits are disclosed for enhanced downside switching of load capacitance. Two PFETs are connected in series as input to the base of an npn type bipolar transistor. The collector and emitter of the bipolar transistor are connected to the circuit output and ground, respectively. One of the series connected PFETs is gated by a predetermined input signal and the second PFET is controlled by the output of an inverter tied to the collector of the bipolar transistor. Upon saturation of the bipolar transistor, the inverter disrupts flow of charge into the base of the transistor and an NFET tied between the base and ground begins to pull charge from the base. A second NFET may be connected to dissipate charge from the collector either through the base or directly to ground. Various circuit modifications are also discussed.

REFERENCES:
patent: 4616146 (1986-10-01), Lee et al.
patent: 4719373 (1988-01-01), Masuda et al.
patent: 4813020 (1989-03-01), Iwamura et al.
patent: 4910416 (1990-03-01), Salcone
patent: 4926069 (1990-05-01), Yamazaki
patent: 4970414 (1990-11-01), Ruth, Jr.
patent: 5001365 (1991-03-01), Murabayashi et al.
patent: 5027009 (1991-06-01), Urakawa

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