BiCMOS compacted logic array

Details BiCMOS compacted logic array BiCMOS compacted logic array

1995-03-27

2000-06-27

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257206, 257370, 257378, 257499, H01L 2710

Patent

active

060810041

ABSTRACT:
A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

REFERENCES:
patent: 4884118 (1989-11-01), Hui et al.
"A 200k Gate 0.8 .mu.m Mixed CMOS/BiCMOS Sea-of-Gates", IEEE International Solid-State Circuits Conference, Session 5, Feb. 15, 1990, Y. Enomoto et al., IEEE 1990.
A 350 ps 50K 0.8 .mu.m BiCMOS Gate Array With Shared Bipolar Cell Structure, H. Hara et al., IEEE 1989 Custom Integrated Circuits Conference, IEEE 1990.
Proceedings of the IEEE 1987 Custom Integrated Circuits Conference, May 4, 1987, Oregon, U.S.A., pp. 190-194, "A 9100 Gate ECL/TTL Compatible BICMOS Gate Array", Liang-Tsai Lin et al., pp. 192-193, IEEE 1987 Custom Integrated Circuits Conference.

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