BICMOS cache TAG having ECL reduction circuit with CMOS output

Details BICMOS cache TAG having ECL reduction circuit with CMOS output BICMOS cache TAG having ECL reduction circuit with CMOS output

1994-09-15

1995-12-05

Nelms, David C.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518907, 395403, G11C 1500

Patent

active

054735610

ABSTRACT:
A cache TAG RAM (25) includes a reduction circuit (39) for comparing match signals from a plurality of exclusive OR logic circuits (33, 34) and provides a hit signal when all of the TAG address bits of a stored TAG address is the same as input address bits. The reduction circuit (39) provides a miss signal when any one or more of the bits of the stored TAG address is not the same as the corresponding bits of the input address bits. In one embodiment, the reduction circuit (39) uses a plurality of transistors (77, 78) coupled to a conductor (75) for discharging the conductor (75) if one of the exclusive OR logic circuits (33, 34) indicates a miss. In another embodiment, the reduction circuit (39") charges the conductor. The comparison can be made using signals having small signal swing at high speed, and a reference voltage is not needed for the comparison.

REFERENCES:
patent: 5218567 (1993-06-01), Suzuki et al.
patent: 5241510 (1993-08-01), Kobayashi et al.
patent: 5253197 (1993-10-01), Suzuki et al.
patent: 5329632 (1994-07-01), Lee et al.

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