BICMOS buffer circuit

Details BICMOS buffer circuit BICMOS buffer circuit

1989-06-27

1990-06-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307443, 307279, H03K 1901, H03K 19003, H03K 19082, H03K 19094

Patent

active

049374800

ABSTRACT:
A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance. In still another example, in a CMOS NOR ciruit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.

REFERENCES:
patent: 4695750 (1987-09-01), Hara et al.
patent: 4740718 (1988-04-01), Matsui
patent: 4779014 (1988-10-01), Masuoka et al.
patent: 4858191 (1989-08-01), Higuchi et al.

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