Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – In integrated structure
Reexamination Certificate
2000-11-20
2003-09-23
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
In integrated structure
C257S471000, C257S484000, C257S369000, C257S401000, C257S382000, C257S384000
Reexamination Certificate
active
06624493
ABSTRACT:
TECHNICAL AREA
The present invention relates to semiconductor devices, and more particularly comprises semiconductor devices which include junctions that rectify when the semiconductor is doped either N or P-type by either metallurgical or field induced means, as well as similar means for limiting parasitic current flow in semiconductor substrates. Semiconductor substrates can, prior to the fabrication of present invention semiconductor devices therein, be essentially intrinsic, or substantially homogeneously contain N and P-type dopants at substantially equal levels, (ie. compensated), or simultaneously substantially homogeneously contain N and P-type dopants at different levels, or be doped a single N or P doping type, and can include functional combinations thereof. A preferred embodiment is formed in intrinsic or substantially compensated semiconductor and is a simple to fabricate single device which provides operational characteristics similar to conventional dual device CMOS, under described biasing schemes.
BACKGROUND
MOSFETS, CMOS, gate voltage controlled direction of rectification, and single device inverting and single device non-inverting MOS semiconductor devices which demonstrate operating characteristics similar to those of multiple device Complementary Metal Oxide Semiconductor (CMOS) systems have been previously described in U.S. Pat. No. 5,663,584 to Welch, and said 584 Patent is incorporated hereinto by reference. Semiconductor devices described in said 584 Patent operate on the basis that materials exist which produce a rectifying junction with semiconductor channel regions when they are doped either N or P-type, whether said doping is achieved via metallurgical or field induced means. Said materials typically form junctions that are termed “Schottky barrier” junctions with semiconductors, (in contrast to P-N Junction), however, said terminology is not to be considered limiting to the present invention based upon technical definitions of the terminology “Schottky barrier”, and where the terminology “Schottky barrier” junction is utilized in this Disclosure it is to be understood that it is used primarily to distinguish a junction described thereby from “P-N” junctions, and more particularly to identify junctions between a semiconductor and element(s) which are rectifying whether N or P-type Doping is present in the semiconductor, and whether said doping is present as the result of metallurgical or field induced means.
Another U.S. Pat. No. 5,760,449 to Welch describes Source Coupled Regeneratively Switching CMOS formed from a seriesed combination of N and P-Channel MOSFTES which each demonstrate the special operating characteristics of conducting significant current flow only when the Drain and Gate of a 449 Patent MOSFET are of opposite polarity, and the Gate polarity is appropriate to invert a channel region. Said 449 Patent is incorporated hereinto by reference, as is U.S. Pat. No. 6,091,128 to Welch, (which describes prevention of parasitic current flow in semiconductor substrates), and provisional Applications and Ser. Nos. 60/081,705 and 60/090,565. Also disclosed are Patents to Lepselter, U.S. Pat. No. 4,300,152; Koeneke et al., U.S. Pat. No. 4,485,550; Welch, U.S. Pat. No. 4,696,093; Mihara et al., U.S. Pat. No. 5,049,953; Homna et al. U.S. Pat. No. 5,177,568; and Nowak, U.S. Pat. No. 5,250,834. A Japanese Patent to Shirato, No. 04056360 is also disclosed as it describes the presence of conducting material in a MOSFET Channel region, (in contrast to a current limiting material as in the present invention).
A relevant article titled “SB-IGFET: An Insulated Gate Field Effect Transistor using Schottky Barrier Contacts for Source and Drain”, by Lepselter & Sze, Proc. IEEE, 56, January 1968, pp. 1400-1402, is also identified in said 584 Patent. Further, a paper by Lebedov & Sultanov, titled “Some Properties of Chromim-Doped Silicon”, Soviet Physics, Vol. 4, No. 11, May 1971 is identified as it discusses formation of a rectifying junction by diffusion of chromium into P-type Silicon. A paper by Hogeboom & Cobbold, titled “Etched Schottky Barrier MOSFETS Using A Single Mask, Electronics Letters, Vol. 7, No. 5/6, (March 1971) is also included as it describes formation of Schottky barrier MOSFETS by deposition of Aluminum onto semiconductor. Articles which are incorported by reference hereinto, and which describe fabrication of non-scale conventional Schottky-barrier MOSFETS are “Sub-40 nm PtSi Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistors”, Wang, Snyder & Tucker, Appl. Phys. Lett., Vol. 74, No. 8, (Feb. 22, 1999); and “Experimental Investigation of a PtSi Source and Drain Filed Emission Transistor”, Synder, Helms & Nishi, Appl. Phys. Lett. 67(10) (Sep. 4, 1995). While not being a point of Patentability, it is to be understood that present invention systems whi“Sub-40 nm PtSi Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistors”, Wang, Snyder & Tucker, Appl. Phys. Lett., Vol. 74, No. 8, (Feb. 22, 1999); and “Experimental Investigation of a PtSi Source and Drain Filed Emission Transistor” Synder, Helms & Nishi, Appl. Phys. Lett. 67(10) (Sep. 4, 1995). ch incorporate sidewall spacers, as taught in said directly foregoing references, are to be considered within the scope of the present invention as claimed. Also mentioned, and included herein by reference for general insight to semiconductor circuits and systems, is a book titled “Microelectronic Circuits” by Sedra and Smith, Saunders College Publishing, 1991. Likewise mentioned, and included herein by reference for the purpose of providing insight into semiconductor device fabrication, is a book titled “Physics and Technology of Semiconductor Devices”, by Grove, John Wiley & Sons, 1967; and a book titled “Electronic Materials Science: For Integrated Circuits in Si and GaAs”, Mayer & Lau, MacMillan, 1990.
Even in view of the cited Welch U.S. Pat. Nos. 5,663,584; 5,760,449 and 6,091,128 Patents, and co-pending CIP applications derived therefrom which describe inverting and non-inverting single device equivalents to conventional CMOS, regeneratively switching N and P-Channel source coupled CMOS, and the blocking of parasitic current flows in semiconductor systems by use of material which forms rectifying junctions with either N or P-type semiconductor whether said doping is metallurgically or field induced; there remains need for clarification and description of parasitic current limitation, and of biasing and switching operational characteristics of single device equivalents to CMOS, particularly where essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels; essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; and containing a single metallurgical doping type, substantially compensated, or lightly doped, semiconductor is beneficially utilized as semiconductor substrate material.
DISCLOSURE OF THE INVENTION
The present invention is primarily a semiconductor device in a semiconductor substrate, comprising at least one junction which is formed by introduction of typically, (though not necessarily), non-semiconductor substrate material(s) to said semiconductor substrate, wherein said typically non-semiconductor substrate material(s) form a rectifying junction with either N and P-type semiconductor, whether said doping is metallurgically or field induced. Said non-semiconductor components can be any functional material(s) or dopants entered to a semiconductor substrate by, for instance, a procedure comprising vacuum deposition, ion-implantation and/or pre-deposition and diffusion, each accompanied by appropriate annealing. And, it is noted that the semiconductor substrate can, prior to the fabrication of present invention semiconductor devices therein, be initially essentially intrinsic or substantially homogeneously contain metallurgical N and P-type dopants at substantially the same levels, (ie. be substantia
Loke Steven
Welch James D.
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