Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-09-22
2002-04-09
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S330000
Reexamination Certificate
active
06369641
ABSTRACT:
TECHNICAL FIELD
This invention relates to systems and methods for generating a negative bias.
BACKGROUND
In depletion mode devices, such as certain field effect transistors (FETs) and high electron mobility transistors (HEMTs), a conducting channel exists at zero gate bias, and a negative gate voltage is required to turn the device off. Such “normally on” devices are called depletion mode devices because gate voltage is used to deplete the channel that exists at equilibrium. For example, in a FET with an n
+
source and drain and a p-type substrate biased at zero volts, a channel (or depletion layer) exists between the FET terminals and the substrate. In some applications, the channel may be depleted and the FET turned off, by applying a negative bias between the gate and the substrate. In other applications, a negative bias may be applied to the FET substrate to reduce the body effect, decrease the depletion capacitance and increase the switching speed of the FET.
Many different circuits for producing a negative bias have been proposed. Both off-chip (or external) and on-chip negative bias circuits have been developed. A typical on-chip negative bias circuit for biasing resistive loads, such as the circuit substrate, includes a ring oscillator and a diode rectifier. A low pass filter typically is used with such on-chip circuits to reduce the ripple voltage produced at the output of the diode rectifier. Still other biasing circuits have been proposed.
SUMMARY
The invention features a scheme (systems and methods) for biasing high impedance loads (e.g., the input gate of a FET amplifier or a HEMT amplifier).
In one aspect, the invention features a bias circuit comprising a rectifier, a negative bias level setter, and a negative bias extractor. The rectifier has a rectifier input and a rectifier output. The rectifier is configured to produce at the rectifier output a negative rectified voltage signal from an alternating input signal applied at the rectifier input. The negative bias level setter couples to the rectifier output and provides a path for current establishing the negative rectified voltage signal produced at the rectifier output. The negative bias extractor has an extractor output and an extractor input coupled to the rectifier output. The negative bias extractor is configured to produce at the extractor output a substantially constant negative bias signal from the negative rectified voltage signal produced at the rectifier output.
Embodiments in accordance with this aspect of the invention may include one or more of the following features.
The negative bias level setter preferably is configured to substantially block the flow of current through the negative bias level setter current path during a positive cycle of the alternating input signal. The negative bias level setter may comprise a diode oriented for forward current flow toward the rectifier output. The negative bias level setter may further comprise a second diode coupled in series with the first diode and oriented for forward current flow toward the rectifier output. The negative bias level setter may further comprise a resister coupled in series with the diode.
The rectifier may comprise a diode coupled to the rectifier input and oriented for forward current flow away from the rectifier input. The rectifier may further comprise a second diode coupled to the rectifier input and oriented for forward current flow toward the rectifier input. The rectifier may comprise a transistor with a control terminal coupled to the rectifier input and oriented for forward current flow away from the rectifier input.
The negative bias extractor preferably comprises a capacitor coupled to the rectifier output in parallel with the negative bias level setter. The negative bias extractor may further comprise a resistor coupled between the rectifier output and the extractor output.
A capacitor may be coupled between the rectifier input and a source of the alternating input signal applied at the rectifier input.
In another aspect, the invention features a method of producing a bias. A negative rectified voltage signal is produced from an alternating input signal. A path for current establishing the negative rectified voltage signal is provided. A substantially constant negative bias signal is produced from the negative rectified voltage signal.
Embodiments in accordance with this aspect of the invention may include one or more of the following features.
The flow of current through the current path establishing the negative rectified voltage signal preferably is substantially blocked during a positive cycle of the alternating input signal. Charge preferably is stored during a negative cycle of the alternating input signal. The negative rectified voltage signal preferably is low pass filtered. A direct current component of the alternating input signal preferably is substantially blocked before producing the negative rectified voltage signal.
In another aspect, the invention features a bias circuit comprising a biasing output coupled between a positive voltage source and a negative voltage source, and a switching circuit coupled between the positive voltage source and the biasing output. The switching circuit is configured to define two or more different current paths through the switching circuit and thereby produce two or more respective biasing states at the biasing output.
Embodiments in accordance with this aspect of the invention may include one or more of the following features.
The switching circuit preferably is configured to define a relatively low resistance current path, a relatively high resistance current path, and a cutoff current path. The switching circuit preferably comprises a first switch coupled in series with a second switch and a resistor coupled across the current terminals of the first switch. The bias circuit may further comprise a stabilizer having an input that substantially tracks the bias level produced at the biasing output and a negative feedback path coupled to resist changes in the bias level produced at the biasing output. The stabilizer preferably comprises a transistor with a current terminal coupled between the positive voltage source and the biasing output and a control terminal coupled between the biasing output and the negative voltage source.
Among the advantages of the invention are the following.
The invention readily may be incorporated into a microwave monolithic integrated circuit (MMIC) to provide a negative voltage reference without any external components, such as large decoupling capacitors. The invention allows the source terminal of an active device (e.g., an RF FET amplifier) to be DC grounded. This feature increases the drain-source voltage swing of the active device, and improves the power and linearity performance of the active device. In addition, this feature reduces the number of bypassing components and the number of external connections needed to package and active device. The invention also enables different active device operating states to be selected dynamically using positive voltage controls. The inventive switchable bias circuit also improves the stability of the applied bias over variations in device characteristics (e.g., variations in threshold voltage and saturation current).
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.
REFERENCES:
patent: 4208595 (1980-06-01), Gladstein et al.
patent: 4631421 (1986-12-01), Inoue et al.
patent: 4733108 (1988-03-01), Truong
patent: 5559471 (1996-09-01), Black
patent: 5578961 (1996-11-01), Fajen et al.
patent: 5771470 (1998-06-01), Nimmo et al.
Banzer Heinz
McNamara Brian J.
Verweyen Ludger
Infineon Technologies North America Corp.
Kim Jung Ho
LandOfFree
Biasing circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Biasing circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Biasing circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2866534