Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-10-02
2003-01-21
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C365S185200
Reexamination Certificate
active
06509786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a biasing circuit and a semiconductor memory device using the same. More particularly, the present invention relates to a biasing circuit for quickly outputting a stable bias output, and a semiconductor memory device using the same.
2. Description of the Related Art
Conventionally, in a semiconductor memory device, it is important that an access time required to read and write a data is made short so that the whole computer system can be speeded up.
In a conventional semiconductor memory device such as s nonvolatile memory and a ROM, a data of 1 bit is stored in a memory cell. A predetermined bias voltage is applied to the drain of a transistor in the memory cell when the stored data should be read out. At this time, the stored data is determined to be “0” or “1” based on whether or not a drain current is larger than a predetermined value. Generally, the drain voltage is increased as the drain current of the transistor becomes larger. Therefore, if the bias voltage applied to the drain of the memory cell transistor is not stable when the stored data should be read out, the drain current is also not stable. As a result, it is not possible to correctly determine whether the drain current is larger than the predetermined value.
In recent years, the data is sometimes stored in the memory cell in the form of multiple bits, e.g., in the form of 4 bits. In such a multi-bit memory device, the stored data is determined based on the small difference in the drain current. Therefore, the bias voltage applied to the drain of the memory cell transistor must be strictly set to a predetermined value. For this purpose, the performance of the sense amplifier is given as one of the important factors to determine the access time of the semiconductor memory device. For this reason, various studies have been accomplished so far. For example, the improvement of a sense amplifier for an EPROM is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 63-142596) and Japanese Laid Open Patent Application (JP-A-Heisei 4-353699).
The structures of conventional semiconductor memory devices will be described with reference to
FIGS. 1 and 2
.
FIGS. 1 and 2
are circuit diagrams showing examples of the structures of sense amplifier circuits
100
provided in the conventional semiconductor memory devices.
For example, the conventional semiconductor memory device is a nonvolatile memory which uses a floating gate type MOSFET as a memory cell, as shown in FIG.
1
. The conventional semiconductor memory device is composed of a memory cell array
101
for data storage. Digit lines DL
1
to DL
n
are increased in potential from the ground potential to a predetermined potential so that a data can be read out from the memory cell array
101
by the sense amplifier circuit
100
. The sense amplifier circuit
100
is composed of a sense circuit
10
, a reference circuit
110
, and a data detecting circuit
201
.
Also, the memory cell array
101
is composed of a plurality of word lines WL
1
to WL
m
provided in a row direction and the plurality of digit line DL
1
to DL
n
provided into a column direction. Each of memory cells
113
11
to
113
1n
, . . . ,
113
m1
to
113
mn
is composed of a floating gate type MOSFET and is provided for one of intersections of the plurality of word lines WL
1
to WL
m
and the plurality of digit line DL
1
to DL
n
. That is, the memory cells of m rows and n columns are arranged in a matrix in the memory cell array
101
. The floating gate type MOSFET as the memory cell
113
ji
(j=1 to m, i=1 to n) is connected with the j-th one of the word lines WL
1
to WL
m
at the gate and with the i-th one of the digit lines DL
1
to DL
n
at the drain, and is connected with the ground potential in the source.
Also, a reference cell array
102
is composed of one reference word line WLR provided in a row direction and one reference digit line DLR provided in a column direction. One reference cell
111
with the same structure as the memory cell
113
ji
is provided at an intersection of the reference word line WLR and the reference digit line DLR. The reference cell
111
is connected with the reference word line WLR at the gate, and with reference digit line DLR at the drain and is connected with the ground potential at the source. In this example, the reference word line WLR and the reference DLR are provided to the reference cell array
102
, and only one MOSFET is provided as the reference cell
111
.
A row decoder
104
is connected with the word lines WL
1
to WL
1
in the memory cell array
101
and the column decoder
105
is connected to a column selector
103
. The row decoder
104
and the column decoder
103
are supplied with an address signal (not shown). The row decoder
104
activates one of the word lines WL
1
to WL
m
directly in accordance with the address signal. Also, the column decoder
103
connects one of the digit lines DL
1
to DL
n
with the sense amplifer circuit
100
through the column selector
103
in accordance with the address signal.
The column selector
103
is composed of MOSFETs
107
1
to
107
n
for carrying out digit line selection in response to the output of the column decoder
105
such that one of digit lines DL
1
to DL
n
is selectively connected with the sense circuit
10
. The sources of the MOSFETs
107
1
to
107
n
in the column selector
103
are connected with the respective digit lines DL
1
to DL
n
, and the drains thereof is commonly connected to the sence circuit
10
provided in the sense amplifier circuit
100
.
Further, in the semiconductor memory device, one biasing circuit
20
is provided in the sence circuit
10
for the plurality of digit lines DL
1
to DL
n
. Also, one MOSFET
106
with the same size as MOSFETs
107
1
to
107
n
of the column selector
103
is connected with the reference digit line DLR. The gate of the MOSFET
106
is connected with the power supply voltage. The drain of the MOSFET
106
which is provided for the reference cell array
102
, is connected with the reference circuit
110
.
In
FIGS. 1 and 2
, the word line WL
j
is selected by the row decoder
104
and the digit line DL
i
is selected by the column decoder
105
through the column selector
103
. The case to sense a stored data of the memory cell
113
ji
which is connected with the word line WL
j
and the digit line DL
i
will be described as an example.
As shown in
FIG. 1
, the output terminals of the sense circuit
10
and reference circuit
110
are connected with a data detecting circuit
201
through signal lines LD
i
and LREF, respectively. The data detecting circuit
201
compares a detection voltage VD
i
on the signal line LD
i
and a reference voltage VREF on the signal line LREF, and determines the stored data of the selected memory cell. An output buffer (not shown) is connected on the output side of the data detecting circuit
201
and outputs the stored data from the data detecting circuit
201
.
The memory cells
113
ji
(
113
11
to
113
in
, . . . ,
113
m1
to
113
mn
) and
111
of the nonvolatile memory store data based on whether or not electrons are injected to the floating gate. When the stored data of memory cell
113
ji
should be read, a predetermined voltage is applied to the memory cell
113
ji
by the biasing circuit
20
in the sense circuit
10
. As a result, the stored data is determined based on whether or not a current flows through the selected memory cell
113
ji
. That is, in the memory cell in which electrons have been injected to the floating gate, the drain current does not flow even if a signal with a high level is supplied to the gate when the memory cell
113
ji
is set to a selected state. Oppositely, in the memory cell in which the electrons are pulled out of the floating gate, the drain current flows when the signal with the high level is supplied to the gate of the memory cell transistor in the cell
113
ji
in the selected state. On the other hand, a predetermined reference current alw
Cunningham Terry D.
NEC Corporation
Tra Quan
Young & Thompson
LandOfFree
Biasing circuit for quickly outputting stable bias output... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Biasing circuit for quickly outputting stable bias output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Biasing circuit for quickly outputting stable bias output... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3021230