Biasing circuit for degenerated differential pair

Details Biasing circuit for degenerated differential pair Biasing circuit for degenerated differential pair

2005-02-08

2005-02-08

Urban, Edward F. (Department: 2685)

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

C455S116000, C455S241100, C330S252000, C331S075000

Reexamination Certificate

active

06853838

ABSTRACT:
An improved single-ended input differential pair amplifier stage comprises: 1) a first p-n-p transistor having a base terminal coupled to an input voltage; 2) a first load impedance having a first terminal coupled to a ground reference and a second terminal coupled to a collector of the first p-n-p transistor; 3) a second p-n-p transistor having a base terminal coupled to the ground reference; 4) a second load impedance having a first terminal coupled to a ground reference and a second terminal coupled to a collector of the second p-n-p transistor; 5) an inductor having a first terminal coupled to an emitter of the first p-n-p transistor and a second terminal coupled to an emitter of the second p-n-p transistor; and 6) a constant current source coupled to the emitter of the second p-n-p transistor.

REFERENCES:
patent: 4267516 (1981-05-01), Traa
patent: 4381487 (1983-04-01), Erickson
patent: 4602224 (1986-07-01), Arimoto et al.
patent: 4825173 (1989-04-01), Cornett
patent: 5867778 (1999-02-01), Khoury et al.
patent: 5874865 (1999-02-01), Fairgrieve
patent: 6066991 (2000-05-01), Naito et al.
patent: 6642787 (2003-11-01), Souetinov et al.
patent: 6731693 (2004-05-01), Damgaard

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