Amplifiers – With semiconductor amplifying device – Including field effect transistor
Reexamination Certificate
2000-04-11
2002-04-23
Lee, Benny (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including field effect transistor
C330S302000
Reexamination Certificate
active
06377124
ABSTRACT:
FIELD OF INVENTION
The invention relates to an arrangement biasing depletion mode field effect transistors (FET). The invention is particular directed to radio frequency power amplifiers that are utilised for applications combining the need for high power with a low single-ended supply voltage.
BACKGROUND ART
Depletion mode FET's have a negative threshold or pinch-off voltage. This means that if the source of the transistor is at 0 V, the gate voltage must drop below 0 V to turn the transistor off An ac power amplifier of conventional circuit configuration is shown in FIG.
1
. In this arrangement a FET
100
is coupled by its gate terminal G to an input through a blocking capacitor
110
and to a negative supply voltage Vneg via a resistor
120
. The FET source terminal S is held at ground and the drain terminal D is coupled to the supply voltage Vdd through an inductor (RF choke)
130
and to the output through a resistor
140
and a further blocking capacitor
150
. The output power in this arrangement is controlled by the gate voltage of the FET
100
. The FET is “on” when the voltage at the gate G equals that at the source S, i.e. when the gate is at ground. To switch the FET “off”, the gate must be pulled more negative than the source S by a specified amount; the required voltage difference depends on the type of FET used. If a negative voltage supply is not available, the amplifier can be turned off only by turning off the positive supply voltage Vdd. In practice this is often accomplished using a switch made up of a p-channel MOSFET.
A further way to bias the FET without using a negative supply voltage is to raise the source voltage. Such an arrangement is shown in FIG.
2
. In this circuit, the gate terminal G of the FET
100
is connected to ground via a resistor R
2
120
, and the source terminal is also connected to ground via a resistor R
1
160
. A bypass capacitor
170
shunts the source resistor R
1
160
. The resistor R
1
160
is suitably selected to enable the FET to be turned off at a desired low gate voltage.
A problem arises with this arrangement when high output power is required but a relatively low supply voltage Vdd is available. This is the case, for example, with GSM mobile phones. In GSM, the power amplifier in mobile phones has a supply voltage of typically 3 V but is required to provide around 3 W output power. As a result, the output impedance of the FET
100
as seen by the next stage is very low, i.e. of the order of a few ohms. For this reason, an impedance matching stage is provided, which in
FIG. 2
consists of an inductor
180
connected at a first terminal to the FET drain D and at the second terminal to the output blocking capacitor
150
, and a capacitor
190
connecting the inductor's second terminal to ground. However, another, more problematic, consequence of the low supply voltage and high required output power are the high currents in the transistor. For example, in GSM, peak currents of 3A are common. In order for the bypass capacitor
170
to be effective in sinking these currents, it must be very large. For example, with peak currents of
3
A in the transistor, a capacitance of around 15 nF would be required. Such a capacitor cannot easily be implemented on chip. It should be noted that for radio frequency (RF) and specifically microwave applications, the capacitor
170
will always have to be large, regardless of the value of the resistor
160
. At these frequencies, the resistor
160
will have a significant series inductance. Thus even if the resistance was set to a fraction of an ohm, the bypass capacitor would still have to be prohibitively large for on-chip implementations.
It is thus an object of the present invention to provide an amplifier arrangement that overcomes the problems associated with prior art configurations.
It is a further specific object of the present invention to provide an amplifier arrangement that is suitable for use with a low, single-ended power supply and for RF applications. Preferably, the arrangement should lend itself easily to on-chip implementation.
SUMMARY OF INVENTION
According to the present invention the above object is achieved in a power amplifier including a FET with an input coupled to the gate terminal and an output coupled to the drain terminal via an impedance matching stage connected between the drain terminal and ground. A source biasing element shunted by a bypass capacitor couples the source terminal to ground. According to the invention, a common terminal is provided between the transistor source and the impedance matching stage and this common terminal is connected to ground through the source biasing element
By providing a common terminal between the impedance matching components and the transistor source, the impedance looking into the source terminal is effectively defined by the impedance matching components. The peak currents passing through a source bypass capacitor element can thus be considerably reduced, specifically to a level which allow the capacitor to be of a more manageable size, and to be implemented on chip.
The source biasing element may be a resistor, which can be selected to alter the gate-source voltage of the transistor, and so enable the transistor to be turned off.
In a further embodiment of the invention, the source biasing element is a second field effect transistor, preferably a MOSFET, operating as a voltage controlled resistor. In addition to biasing the power amplifier, the second FET can also be used to regulate the power amplifier. Specifically, the current through the power amplifier can be controlled by varying the gate voltage of the second FET.
In a preferred arrangement, the second FET serves as a dc-to-dc converter, at least for low output powers of the amplifier, wherein it is switched and its voltage filtered. In this way, the efficiency of the arrangement is greatly enhanced. The solution is also cost-effective as a single second FET is utilised as a voltage controlled resistor at high output powers and as a switch at low output powers.
According to the invention, the amplifier arrangement is preferably included as at least one stage of a power amplifier for a mobile phone.
The invention also concerns a mobile phone incorporating a power amplifier as described above.
REFERENCES:
patent: 4631493 (1986-12-01), Vendelin et al.
patent: 5767756 (1998-06-01), Hwang
patent: 6163222 (2000-12-01), Kobayashi
patent: 07240638 (1995-09-01), None
patent: 08078969 (1996-03-01), None
patent: 09283710 (1997-10-01), None
Choe Henry
Jenkens & Gilchrist P.C.
Lee Benny
Telefonaktiebolaget LM Ericsson
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