Biasing and sizing of the MOS transistor in weak inversion for l

Details Biasing and sizing of the MOS transistor in weak inversion for l Biasing and sizing of the MOS transistor in weak inversion for l

1999-04-15

2000-12-05

Pascal, Robert

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

330288, H03F 304

Patent

active

061572594

ABSTRACT:
Methods and circuits are disclosed for low voltage (1.5 Volt and below) CMOS circuits, offering good transconductance and current driving capabilities. These goals are achieved by biasing CMOS transistors in the weak inversion region, by utilizing multiple unit-sized transistors with a fixed gate width to gate length ratio, and by maintaining a uniform threshold voltage of each unit-sized transistor. The required transistor size is obtained by parallel connection of several unit-sized transistors, such that `n` unit sized transistors carry the required current of `n` units. The methods and circuits disclosed eliminate deviation of the output current of current mirrors caused by threshold voltage mismatch. Disclosed are a current mirror and two typical amplifiers as examples of weak inversion design.

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Vittoz et al., "CMOS Analog Integrated Circuits Based on Weak Inversion Operation", IEEE Journal of Solid-State Circuits, vol. SC-12, No. 3, Jun. 1977.
Grotjohn et al., "A Parametric Short-Channel MOS Transistor Model for Subthreshold and Strong Inversion Current", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 1, Feb. 1984.

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